IRC log search results for git

• 2019-09-15 (Sunday):

  shorne	https://github.com/stffrdhrn/binutils-gdb/commit/10c9de573d40fe8654f33cd6f02a822a0d0de13f	20:56
  tpb	Title: or1k: add tls mask to handle multiple model access · stffrdhrn/binutils-gdb@10c9de5 · GitHub (at github.com)	20:56

• 2019-09-12 (Thursday):

  shorne	ysionneau: The gcc tests are run with dejagnu, which includes sim + qemu, scripts are here: https://github.com/stffrdhrn/or1k-utils/blob/master/site.exp	09:55
  tpb	Title: or1k-utils/site.exp at master · stffrdhrn/or1k-utils · GitHub (at github.com)	09:55
  shorne	For glibc, I am building with the scripts from here: https://github.com/stffrdhrn/or1k-utils/tree/master/glibc	09:56
  tpb	Title: or1k-utils/glibc at master · stffrdhrn/or1k-utils · GitHub (at github.com)	09:56

• 2019-09-11 (Wednesday):

  shorne	Well, yes,  there is a glibc test thought, that uses these macros: https://github.com/stffrdhrn/or1k-glibc/blob/upstream-rebase/sysdeps/or1k/tls-macros.h	10:29
  shorne	specifically https://github.com/stffrdhrn/or1k-glibc/blob/upstream-rebase/sysdeps/or1k/tls-macros.h#L60-L64	10:29
  shorne	https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=bfd/elf32-or1k.c;h=0d1336ceaccdc2a861c9bbb45b20c0931df0e0d2;hb=HEAD#l1625	10:33
  ysionneau	the culprit seems to be: https://git.uclibc.org/uClibc/commit/?id=6cbeaa5dd11a1b506a8a97b4dfb4e632240f9953	11:49

• 2019-09-08 (Sunday):

  ysionneau	a glims of what I use for openrisc: https://github.com/fallen/uclibc-ng-ci/tree/master/conf/or1k	18:00
  tpb	Title: uclibc-ng-ci/conf/or1k at master · fallen/uclibc-ng-ci · GitHub (at github.com)	18:00

• 2019-08-23 (Friday):

  ysionneau	ok I've got my answer, it is there: https://github.com/openrisc/doc/raw/master/openrisc-arch-1.3-rev1.pdf	10:51
  shorne	diff --git a/libc/sysdeps/linux/or1k/or1k_clone.S b/libc/sysdeps/linux/or1k/or1k_clone.S	16:47
  shorne	Note, in the glibc port I am working on fixing up I dont get this issue and the code is the same pretty much: https://github.com/stffrdhrn/or1k-glibc/blob/upstream-rebase/sysdeps/unix/sysv/linux/or1k/or1k_clone.S	16:53
  tpb	Title: or1k-glibc/or1k_clone.S at upstream-rebase · stffrdhrn/or1k-glibc · GitHub (at github.com)	16:53
  shorne	https://github.com/stffrdhrn/or1k-glibc/blob/upstream-rebase/sysdeps/or1k/dl-machine.h#L191	16:56
  tpb	Title: or1k-glibc/dl-machine.h at upstream-rebase · stffrdhrn/or1k-glibc · GitHub (at github.com)	16:56

• 2019-08-03 (Saturday):

  ZipCPU	(It referenced the github location)	20:16

• 2019-07-28 (Sunday):

  shorne	https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=gdb/or1k-tdep.c;h=8f6f6e196090f0c39d3f347a41531b4eeebd37b0;hb=HEAD#l479	18:44
  tpb	Title: sourceware.org Git - binutils-gdb.git/blob - gdb/or1k-tdep.c (at sourceware.org)	18:44

• 2019-04-02 (Tuesday):

  shorne	You can run some examples using, or1k-tests... we have some examples in https://github.com/openrisc/or1k_marocchino/blob/master/.travis.yml	01:41
  tpb	Title: or1k_marocchino/.travis.yml at master · openrisc/or1k_marocchino · GitHub (at github.com)	01:41

• 2019-01-12 (Saturday):

  shorne	https://github.com/openrisc/mor1kx/issues/71	16:12
  tpb	Title: Espresso Tests Failing · Issue #71 · openrisc/mor1kx · GitHub (at github.com)	16:12
  shorne	First test failing is, https://github.com/openrisc/or1k-tests/blob/master/native/or1k/or1k-alignillegalinsn.S	16:12
  tpb	Title: or1k-tests/or1k-alignillegalinsn.S at master · openrisc/or1k-tests · GitHub (at github.com)	16:12

• 2019-01-07 (Monday):

  lau-cris	hello there, I have observed that someone (who?) posted the obsolete version 1.0.3  of openverifla (my project) on github (freecores). The current version of openverifla is 2.3 (on opencores.org); I kindly ask you to delete version 1.0.3 from github.	08:44

• 2018-11-14 (Wednesday):

  ZipCPU	You might have a better chance finding him on gitter than on freenode	22:40

• 2018-10-24 (Wednesday):

  * alown_cara looks on github		06:54
  ZipCPU	https://github.com/ZipCPU/autofpga	06:54
  ZipCPU	I have used this with an iCE40 design, https://github.com/ZipCPU/icozip	06:58
  ZipCPU	I've also used it with https://github.com/ZipCPU/tinyzip, just ... the pre-production hardware I have doesn't seem to be supported anymore, so I've never loaded this design and proven that it works	06:59
  ZipCPU	Check out slide 26 (internal marking) of https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf.pdf	07:19

• 2018-10-23 (Tuesday):

  alown_cara	Sorry to intrude, I have come here from the note on http://freecores.github.io	12:46
  ZipCPU	alown_cara: There's a wb_intercon project that olof might be able to help you with, but you'd need to ask on gitters librecores/Lobby	16:35

• 2018-09-24 (Monday):

  ZipCPU	formruga: You might want to try the gitter (not freenode) chat room, librecores/Lobby	19:32

• 2018-08-05 (Sunday):

  shivm28[m]	shorne: In the final evaluation, we are supposed to submit a detailed summary of work done with PRs and commits. Oh, yes a blog should work fine. I was a bit confused between blog vs GitHub gist.	23:48

• 2018-08-04 (Saturday):

  shivm28[m]	I think a public GitHub gist might be good. What to do you think?	05:51

• 2018-07-13 (Friday):

  shorne	which comes from: http://repo.or.cz/openocd.git/blob/HEAD:/src/target/openrisc/or1k.c#l52	22:20
  shorne	https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=gdb/remote.c;h=a81d67e5ede4ba1f9c639527d2eb80de60c7e055;hb=HEAD#l8192	22:31

• 2018-07-12 (Thursday):

  shivm28[m]	shorne: I am working on code for the 'g' command. I meant to read register number 1024 from group 0  using the CDM client class. OpenOCD provides register map: https://github.com/ntfreak/openocd/blob/d04254196e383965627d4eab805f9b1b93240e69/src/target/openrisc/or1k.c#L53	12:40
  shivm28[m]	Here, GDBserver asks for the specific core register list:  http://repo.or.cz/openocd.git/blob/HEAD:/src/server/gdb_server.c#l1194	12:45
  shivm28[m]	I have followed a similar approach but without providing any register map: https://github.com/shivmgg/osd-sw/blob/86cef0fd98be352f7f34443b54ada3fd23c6432c/src/libosd/gdbserver.c#L391	12:48

• 2018-07-10 (Tuesday):

  gnanukrishna	https://github.com/openrisc/mor1kx/blob/master/doc/mor1kx.asciidoc	15:45

• 2018-06-29 (Friday):

  shivm28[m]	Here's the link for the PR: https://github.com/opensocdebug/osd-sw/pull/20	04:20

• 2018-06-20 (Wednesday):

  shivm28[m]	I went through the gdbserver in both qemu and openocd. IN QEMU,  connection between gdb and gdbserver are implemented as: https://git.qemu.org/?p=qemu.git;a=blob;f=gdbstub.c#l1823	13:53

• 2018-06-17 (Sunday):

  shorne	https://github.com/stffrdhrn/gcc/releases/tag/or1k-9.0.0-20180613	10:28
  shorne	GNU gdb (GDB) 8.1.50.20180521-git	10:33
  shivm28[m]	It worked. Now, I get: GNU gdb (GDB) 8.1.50.20180521-git	10:39

• 2018-06-08 (Friday):

  shorne	https://stffrdhrn.github.io/software/embedded/openrisc/2018/02/03/openrisc_gcc_rewrite.html	17:03
  shorne	https://stffrdhrn.github.io/software/embedded/openrisc/2018/06/08/gcc_stack_frames.html	17:04
  shorne	https://stffrdhrn.github.io/software/embedded/openrisc/2018/06/03/gcc_passes.html	17:04

• 2018-05-09 (Wednesday):

  shorne	https://gist.github.com/stffrdhrn/77201199f1e7d90a50278f1f8bd5ec57	09:52

• 2018-05-02 (Wednesday):

  wallento	can we followup later here: https://gitter.im/optimsoc/Lobby	14:20
  shivm28[m]	So, I can discuss all my doubts here: https://gitter.im/optimsoc/Lobby, right?	14:27

• 2018-04-17 (Tuesday):

  mor1kx	[mor1kx] olofk pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/a9a01c009ea2b24764973560fde4a9855f4ba95d	01:56
  mor1kx	[mor1kx] olofk closed pull request #57: Fix compiling on modelsim after iverilog fixes (master...modelsim-fix) https://github.com/openrisc/mor1kx/pull/57	01:57

• 2018-04-01 (Sunday):

  shorne	https://github.com/stffrdhrn/gcc/commit/b18703180b1364d4b00a83686bee7d7fddbcfdb2	17:30

• 2018-03-19 (Monday):

  shorne	https://github.com/stffrdhrn/gcc/tree/or1k-port	17:21

• 2018-03-17 (Saturday):

  shorne	If anyoen has time to work on cleaning up and upstreaming these binutils patches it would be good https://github.com/stffrdhrn/binutils-gdb/commits/or1k-2.30	05:29

• 2018-02-09 (Friday):

  futarisIRCcloud	shorne: Cool. http://stffrdhrn.github.io/software/embedded/openrisc/2018/02/03/openrisc_gcc_rewrite.html ...  I've worked with gcc, about ~10 years ago, doing MaverickCrunch Co processor stuff for the ep93xx.	08:51
  shorne	futarisIRCcloud: yeah, and http://stffrdhrn.github.io/software/embedded/openrisc/2018/02/03/openrisc_gcc_rewrite.html	18:30

• 2018-01-29 (Monday):

  bandvig	theMagnumOrange: I run my MAROCCHINO pipeline  (https://github.com/bandvig/mor1kx/tree/wb_cdc_75) on 75 MHz easily on Spartan-6.	12:41

• 2018-01-21 (Sunday):

  shorne	https://github.com/stffrdhrn/or1k-utils/blob/master/scripts/make-or1k-linux	04:03

• 2018-01-17 (Wednesday):

  shorne	wbx: can you use this binutils? https://github.com/stffrdhrn/binutils-gdb/tree/or1k-3-rebase-2-29	07:08
  shorne	Marex: the UART I have been using is: https://github.com/stffrdhrn/fusesoc-cores/tree/master/uart16550	07:10
  shorne	https://github.com/olofk/uart16550	07:11
  shorne	most of the code there is not maintained and things that were needed have been moved to github	07:13

• 2018-01-16 (Tuesday):

  wbx	shorne: or1k-7.2.0 branch from your gcc git and binutils 2.29.1 version	14:33

• 2018-01-13 (Saturday):

  mithro	wallento: lccidocker <-- That is you? https://github.com/lccidocker/osstools/blob/master/Dockerfile	23:11

• 2018-01-12 (Friday):

  shorne_	https://github.com/stffrdhrn/or1k-gcc/releases/tag/or1k-7.2.0-20180112	21:04

• 2018-01-09 (Tuesday):

  shorne	https://github.com/stffrdhrn/uclibc-ng/commits/gen-syscall-2	06:46

• 2018-01-06 (Saturday):

  _franck_	https://github.com/r00tkillah/ioh/wiki	16:33

• 2018-01-05 (Friday):

  windel	I think this line in qemu is the root cause: https://github.com/qemu/qemu/blob/master/hw/openrisc/openrisc_sim.c#L112	05:54
  rohitksingh	juliusb: Hi! :) Could you please give any pointers on how we can use this module? https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v Will directly replacing the prontoespresso's fetch module with this one work fine?	06:51
  shorne	wbx: I posted a patch for the nds32 issue https://github.com/stffrdhrn/uclibc-ng/commits/gen-syscall	07:22

• 2018-01-04 (Thursday):

  mor1kx	[mor1kx] stffrdhrn pushed 2 new commits to master: https://github.com/openrisc/mor1kx/compare/0b99d2d712b5...00aab7359435	08:32
  mor1kx	[mor1kx] stffrdhrn opened pull request #58: readme: Update docs on CACHE WIDTH option (master...cache-docs) https://github.com/openrisc/mor1kx/pull/58	08:34
  mor1kx	[mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/70b92df03aa9a0a61ca5df5c001648c68af135d9	09:26

• 2018-01-03 (Wednesday):

  shorne	The master branch here  https://github.com/openrisc/linux is not so good	09:51
  nooga	I'm cloning https://github.com/openrisc/linux.git right now	09:57
  shorne	you can clone : git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git	09:58
  nooga	and it crashes earlier than before https://gist.github.com/nooga/681965dc59f1a4f6207803a8908a4c31	10:24

• 2018-01-02 (Tuesday):

  nooga	shorne_: I followed this tutorial https://github.com/openrisc/tutorials/blob/master/docs/Linux.md	07:20
  nooga	and this happens: https://gist.github.com/nooga/b96b9cb9574ee46ab377bd0d41947075#file-gistfile1-txt-L55	07:23

• 2017-12-31 (Sunday):

  nooga	now, compiled my own kernel and it says this: https://gist.github.com/nooga/5e51c3ae22130a68ab65cb1f28490cea	14:01

• 2017-12-27 (Wednesday):

  rohitksingh	1. Disabling cache disables ties `ibus_burst` signal to low. (https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_cappuccino.v#L550) and (https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_cappuccino.v#L364)	02:45
  rohitksingh	2. FSM uses `READ` state which always deasserts `ibus_req` after receiving `ibus_ack` which takes 1-cycle (https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_cappuccino.v#L418)	02:45

• 2017-12-22 (Friday):

  nooga	I just wrote an elf loader so my vm can load test binaries and ran this https://github.com/openrisc/or1k-tests/blob/master/native/or1k/or1k-mul-basic.S	12:46

• 2017-12-21 (Thursday):

  nooga	https://gist.github.com/nooga/fc973a91772aabf036db94e724233f61 it hits the first ITLBMISS, does this and then loops on IPF	08:08

• 2017-12-19 (Tuesday):

  nooga	I've seen some tests on openrisc github but I looked through the sim configs there and I fear that running these tests would be more work than writing the emu	16:03

• 2017-12-17 (Sunday):

  bandvig	wallento: As I'm not very familiar with git, I would ask do you do this manually or some how automatically?	04:08
  wallento	kind of this one: cd /gitmirror/newlib; git pull upstream master; git push mirror upstream	04:09

• 2017-12-13 (Wednesday):

  mor1kx	[mor1kx] stffrdhrn opened pull request #57: Fix compiling on modelsim after iverilog fixes (master...modelsim-fix) https://github.com/openrisc/mor1kx/pull/57	09:12

• 2017-12-12 (Tuesday):

  shorne_	https://github.com/stffrdhrn/uclibc-ng-test/commits/gen-syscall	05:59
  shorne_	https://github.com/stffrdhrn/uclibc-ng/commits/gen-syscall	05:59

• 2017-12-01 (Friday):

  shorne	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/openrisc/README	04:43

• 2017-11-30 (Thursday):

  jonathan-2	Hey there... I'm planning on building a TTL OpenRISC CPU (yeah, I know it's going to be absolutely huge) but right now I can't even get or1ksim to run. I built or1ksim with the instructions in the github readme file but every time I try to launch a linux kernel with it, the simulator just segfaults.	07:58

• 2017-11-29 (Wednesday):

  mor1kx	[mor1kx] stffrdhrn opened pull request #56: Readme typo fixes (master...readme-typos) https://github.com/openrisc/mor1kx/pull/56	08:15

100 matches in 624 log files with 4145 lines (0.2 seconds).