IRC logs for #openrisc Wednesday, 2017-12-27

--- Log opened Wed Dec 27 00:00:17 2017
rohitksinghHello everyone! I have a question regarding mor1kx cappuccino implementation. So, if I disable cache in cappuccino, looking at the code, cappuccino will take minimum 3-cycles to fetch single instruction.02:41
rohitksingh1. Disabling cache disables ties `ibus_burst` signal to low. ( and (
rohitksingh2. FSM uses `READ` state which always deasserts `ibus_req` after receiving `ibus_ack` which takes 1-cycle (
rohitksinghDid I read the code and infer correctly?02:49
rohitksinghThis is what I get when I disable cache In this screenshot, from start of an instruction fetch to another, cappuccino takes 3-cycles minimum, that too when I give out ack combinatorially. If I give registered ack, it takes minimum 4-cycles.03:37
marex-cloudAnyone at 34C3?05:45
shorne_marex-cloud: maybe olofk? I heard some people mentioning they were going09:42
Marexshorne_: it20:14
Marexshorne_: it's amazing :_)20:14
--- Log closed Thu Dec 28 00:00:19 2017

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