| --- Log opened Wed Dec 27 00:00:17 2017 | ||
| rohitksingh | Hello everyone! I have a question regarding mor1kx cappuccino implementation. So, if I disable cache in cappuccino, looking at the code, cappuccino will take minimum 3-cycles to fetch single instruction. | 02:41 |
|---|---|---|
| rohitksingh | 1. Disabling cache disables ties `ibus_burst` signal to low. (https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_cappuccino.v#L550) and (https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_cappuccino.v#L364) | 02:45 |
| rohitksingh | 2. FSM uses `READ` state which always deasserts `ibus_req` after receiving `ibus_ack` which takes 1-cycle (https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_cappuccino.v#L418) | 02:45 |
| rohitksingh | Did I read the code and infer correctly? | 02:49 |
| rohitksingh | This is what I get when I disable cache https://screenshots.firefoxusercontent.com/images/99cfd108-cba0-4701-b96e-32de803dffca.png In this screenshot, from start of an instruction fetch to another, cappuccino takes 3-cycles minimum, that too when I give out ack combinatorially. If I give registered ack, it takes minimum 4-cycles. | 03:37 |
| marex-cloud | Anyone at 34C3? | 05:45 |
| shorne_ | marex-cloud: maybe olofk? I heard some people mentioning they were going | 09:42 |
| Marex | shorne_: it | 20:14 |
| Marex | shorne_: it's amazing :_) | 20:14 |
| --- Log closed Thu Dec 28 00:00:19 2017 | ||
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