IRC logs for #openrisc Wednesday, 2018-05-02

--- Log opened Wed May 02 00:00:08 2018
wallentoshivm28[m], hi14:02
wallentoyou there?14:02
wallentodid you source the script?14:03
wallentoopensocdebugd should be in the path14:03
shivm28[m]wallento: Hi, thanks for the help. I was following old examples.14:07
shivm28[m]I build my environment using master branch but was following some old version of examples. Figured out the error. Everything worked fine. : }14:08
shivm28[m]wallento: Can I run optimsoc code on Atyls board?14:09
wallentogreat to hear14:10
wallentogenerally yes14:10
wallentoobviously, the devil is in the detail, that it hasn't been ported so far14:11
wallentowhich board was it again?14:11
wallentoah, I found14:11
shivm28[m]Spartan 6 Atlys board14:12
wallentoI see14:12
wallentoso, it should be generally possible14:12
wallentoI don't have access to one and its too expensive to play around14:13
wallentobut I can remotely assist you14:13
shivm28[m]So, I am a GSoC student this year working on adding CDM module and GDB-server to opensocdebug system.14:14
shivm28[m]Just playing around with OptimSoC for a while to get a feel of OpenSoCDebug system.14:15
wallentooh, yeah, hi14:16
wallentoI am co-mentoring you!14:16
wallentois the Atlys board a target board of Tim Videos?14:17
wallentoI see14:18
wallentoI can have a look at it14:18
wallentootherwise it may make more sense to directly dive into the topic14:19
wallentoand integrate the basic opensocdebug into the Tim Video design14:19
shivm28[m]As a first step, I am working on the specification of CDM module. Now, rest of the modules are programmed using SystemVerilog. I was wondering if it is possible to program SV code on Atlys board?14:19
wallentoyes, definetely14:20
wallentocan we followup later here:
wallentoI read that more often14:20
shivm28[m]Just a very trivial question: Should I use any IDE for programming in System Verilog?14:21
wallentoas the editor it is your decision, for synthesis you will need vivado or ISE14:21
shivm28[m]For Atlys board, I need ISE. But ISE doesn't support SystemVerilog. Am I missing something?14:23
wallentooh, really?!14:25
wallentoI will double check14:25
wallentootherwise we may find a good workaround14:25
shivm28[m]Ok cool!!14:25
shivm28[m]So, I can discuss all my doubts here:, right?14:27
wallentoyes, philipp and stafford are also there14:30
wallentoits a bit more convenient than IRC14:30
--- Log closed Wed May 02 19:12:39 2018
--- Log opened Wed May 02 19:12:47 2018
-!- Irssi: #openrisc: Total of 45 nicks [0 ops, 0 halfops, 0 voices, 45 normal]19:12
-!- Irssi: Join to #openrisc was synced in 29 secs19:13
-!- Netsplit *.net <-> *.split quits: mripard, juliusb19:17
-!- stephen_ is now known as Guest2143822:39
--- Log closed Thu May 03 00:00:09 2018

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