IRC logs for #openrisc Friday, 2018-01-05

--- Log opened Fri Jan 05 00:00:14 2018
--- Day changed Fri Jan 05 2018
noogaIs there a way to dump cpu state from or1ksim after each cycle?05:25
windelHi nooga05:52
windelYes05:52
windelYou can use tracing05:53
windelFor example: qemu-system-or1k -kernel baremetal.bin -M or1k-sim -serial stdio -m 16M -D trace.txt -d in_asm,exec,int,op_opt,cpu05:53
windelI am facing issues with the loading of a binary file btw05:54
windelI think this line in qemu is the root cause: https://github.com/qemu/qemu/blob/master/hw/openrisc/openrisc_sim.c#L11205:54
windelAt startup the PC contains a random number.05:55
noogahah05:57
noogaI'm writing my own emu and debugging it when it makes a mistake after millions of instructions is pretty futile05:58
noogamy idea is to dump states from a working emu and my emu05:58
noogaand then compare the two to find places where they diverge05:58
noogathis requires dumping at least the pc and gpr values06:00
windelThat makes sense06:06
windelI think you can use qemu to dump pretty much everything you want06:06
windelAnd then transform it with a script into the format you need to compare it.06:07
noogayup, I think that is what I'm going to try now06:09
noogathanks!06:09
windelMay the source be with you ;)06:30
rohitksinghjuliusb: Hi! :) Could you please give any pointers on how we can use this module? https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v Will directly replacing the prontoespresso's fetch module with this one work fine?06:51
shornewbx: I posted a patch for the nds32 issue https://github.com/stffrdhrn/uclibc-ng/commits/gen-syscall07:22
shorneI started to test but had some issues with th nds32 toolchain build07:22
shornemaybe you have better luck?07:22
noogawow, hehe, register dump -> 400MB08:52
wbxshorne: thx. will test.17:12
-!- Netsplit *.net <-> *.split quits: jonmasters, mithro21:27
-!- mithro_ is now known as mithro21:27
--- Log closed Sat Jan 06 00:00:32 2018

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