IRC logs for #openrisc Wednesday, 2017-09-20

--- Log opened Wed Sep 20 00:00:53 2017
shorneZipCPU|Laptop: on hacker news front page again.  hope thats a good thing :)00:19
stekernthis one, right?
stekernZipCPU|Laptop: good writeup02:32
stekernI would like to see the inverse of it written for hw engineers diving into sw development as well ;)02:33
ZipCPUshorne: stekern: Thank you07:05
ZipCPUstekern: A writeup for hardware engineers diving into S/W development might be useful.07:05
ZipCPUAt this point in time, though, I don't think I could write it.  I'm just not familiar enough (yet) with how h/w engineers (not just digital logic designers) think07:06
mtn2Hi, Anyone implemented mor1kx in Digilent Nexys3/4 FPGA and booted linux?09:17
gdevicHi, I am the author of A-Z80 CPU at OpenCores (,a-z80) read on freecores to try to contact you here on getting some help importing that core to the freecores. Can you help me, or refer to someone who could? Thanks!16:32
shornemtn2: I havent run on any digilent boards, how different is nexys3/4 from the ones we support?18:06
shorneMyabe its the DDR controller, I think our current boards all use a single rate sdram-controller18:07
shornegdevic, if you check the openrisc web history I hope you see this, mithro should be able to help you getting your code on freecores18:09
shorneThere is also now18:09
mafmshorne: gdevic left18:16
--- Log closed Thu Sep 21 00:00:54 2017

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