IRC logs for #openrisc Tuesday, 2017-03-28

--- Log opened Tue Mar 28 00:00:03 2017
-!- [X-Scale] is now known as X-Scale00:49
bandvigstekern: wallento: could you comment my question in (about CPU and Bus clocks relation) ?03:28
wallentobandvig, not to my knowledge03:56
wallentobut it shouldn't be too much of an issue03:56
wallentoone thing I still have on my eternal TODO list is an AXI bus interface unit for mor1kx..03:57
wallentothere it seems more natural03:57
bandvigwallento: thanks for answer. I also guess that with implementation the feature in hardware I have to update initialization routines in libgloss, somewhere in U-Boot and Linux sources. Am I right?04:26
wallentono, I don't think so04:43
wallentothere is nothing that depends on that property04:43
wallentoexcept if UART also runs in another clock domain04:43
bandvigwallento: I think if peripherals (UART, Ethernet etc) continue run on 50 MHz it should be OK.04:53
bandvigwallento:  However, various benchmarks (based on CPU internal timer) have to be corrected.04:53
bandvigwallento:  Also Linux time has become wrong, however it should not damage operation at all.04:53
wallentoyes, thats correct04:53
wallentoI understood that the clock of the core stays the same04:53
wallentobut then its mainly the timer, which becomes visible via the frequency variable in libgloss04:54
bandvigwallento:  I’m not sure that I understand you assumption “that the clock of the core stays the same”. Let me clarify.04:59
bandvigwallento: I’m going to have CPU-core clock is 100 MHz (just for example) and WishBone BUS (and for all peripheral modules) clock is 50 MHz.05:00
wallentoI thought that you want to change the frequency of the bus05:00
wallentobut you mean to change it of the core05:00
wallentowhy not scale wishbone too?05:00
wallentosorry, gtg to a meeting05:00
wallentowill be back in a few hours05:01
bandvigwell, waiting05:01
shorneFYI, trying to boot smp kernel on default de0_nano, interstingly the default for mor1kx is no shadow gprs07:23
shorneso it fails07:23
stekernshorne: you could find some bits and pieces of help from here maybe:
shornestekern: yeah, I have been looking at that.  But wanted to try the basics my self first07:57
shorneI tried just setting .OPTION_RF_NUM_SHADOW_GPR(4)07:57
shorneat the top level invocation in de0_nano... but it seems to not work still07:57
shorneIll try your multicode07:57
shorne(i.e. for now I am just trying to get the smp code to boot on vanilla as possible de0 nano)07:58
shorneJust to ensure no regressions before moving onto actual multicore hardware07:58
dasHello. Complete noob here. What's the easiest tool to disassemble openrisc? I tried IDA and radare2 to no avail15:02
ZipCPUHow about use the or1k-*-objdump -Dr <filename> ? (The * depends upon what compiler you have built.)15:18
dasi'll try to install the toolchain and see what's what. thx15:20
dasOTOH this at best will disassemble but won't help navigate the ASM code right?15:23
daslike r2 would15:23
ZipCPUI'm not familiar with r2, and ... you asked for a tool to disassemble a project.15:23
dastrue15:26 handles openrisc but it's not enough to help me reverse15:27
ZipCPUReverse engineering is a time consuming and painful field of engineering.  Be prepared to pay for whatever you wish to do in your own sweat.15:28
dasofc that's the point15:28
dasI wouldn't need help for x86/arm15:29
shornedas: r2 is used as the frame pointer16:39
shornethere are good docs on it here16:39
shorneAlso, you can get toolchains for linux here;
shornejust get or1k-elf-5.4.0...16:40
shornestekern: is there anything from your mor1kx/multicore branch that is not upstream?16:52
stekernumm, I don't think so16:58
shornestekern: I rebased the orpsoc-cores on latest, had to fix some things up in de0_nano-multicore17:53
shornestuck it it on my de0_nano17:53
shorneand booted the kernel17:54
shorneit getst to here17:54
shornesmp: Bringing up secondary CPUs ...17:54
shorneCPU1: Booted secondary processor17:54
shorneCPU: OpenRISC-10 (revision 0) @50 MHz17:54
shorneso... almost there17:54
shorneits using the openrisc/mor1kx17:55
--- Log closed Wed Mar 29 00:00:05 2017

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