| --- Log opened Tue Mar 28 00:00:03 2017 | ||
| -!- [X-Scale] is now known as X-Scale | 00:49 | |
| bandvig | stekern: wallento: could you comment my question in http://juliusbaxter.net/openrisc-irc/%23openrisc.2017-03-27.log.html (about CPU and Bus clocks relation) ? | 03:28 |
|---|---|---|
| wallento | bandvig, not to my knowledge | 03:56 |
| wallento | but it shouldn't be too much of an issue | 03:56 |
| wallento | one thing I still have on my eternal TODO list is an AXI bus interface unit for mor1kx.. | 03:57 |
| wallento | there it seems more natural | 03:57 |
| bandvig | wallento: thanks for answer. I also guess that with implementation the feature in hardware I have to update initialization routines in libgloss, somewhere in U-Boot and Linux sources. Am I right? | 04:26 |
| wallento | no, I don't think so | 04:43 |
| wallento | there is nothing that depends on that property | 04:43 |
| wallento | except if UART also runs in another clock domain | 04:43 |
| bandvig | wallento: I think if peripherals (UART, Ethernet etc) continue run on 50 MHz it should be OK. | 04:53 |
| bandvig | wallento: However, various benchmarks (based on CPU internal timer) have to be corrected. | 04:53 |
| bandvig | wallento: Also Linux time has become wrong, however it should not damage operation at all. | 04:53 |
| wallento | yes, thats correct | 04:53 |
| wallento | I understood that the clock of the core stays the same | 04:53 |
| wallento | but then its mainly the timer, which becomes visible via the frequency variable in libgloss | 04:54 |
| bandvig | wallento: I’m not sure that I understand you assumption “that the clock of the core stays the same”. Let me clarify. | 04:59 |
| bandvig | wallento: I’m going to have CPU-core clock is 100 MHz (just for example) and WishBone BUS (and for all peripheral modules) clock is 50 MHz. | 05:00 |
| wallento | I thought that you want to change the frequency of the bus | 05:00 |
| wallento | but you mean to change it of the core | 05:00 |
| wallento | why not scale wishbone too? | 05:00 |
| wallento | sorry, gtg to a meeting | 05:00 |
| wallento | will be back in a few hours | 05:01 |
| bandvig | well, waiting | 05:01 |
| shorne | FYI, trying to boot smp kernel on default de0_nano, interstingly the default for mor1kx is no shadow gprs | 07:23 |
| shorne | so it fails | 07:23 |
| shorne | enabling | 07:23 |
| stekern | shorne: you could find some bits and pieces of help from here maybe: https://github.com/skristiansson/orpsoc-cores/tree/multicore/systems/de0_nano-multicore | 07:54 |
| shorne | stekern: yeah, I have been looking at that. But wanted to try the basics my self first | 07:57 |
| shorne | I tried just setting .OPTION_RF_NUM_SHADOW_GPR(4) | 07:57 |
| shorne | at the top level invocation in de0_nano... but it seems to not work still | 07:57 |
| shorne | Ill try your multicode | 07:57 |
| shorne | (i.e. for now I am just trying to get the smp code to boot on vanilla as possible de0 nano) | 07:58 |
| shorne | Just to ensure no regressions before moving onto actual multicore hardware | 07:58 |
| das | Hello. Complete noob here. What's the easiest tool to disassemble openrisc? I tried IDA and radare2 to no avail | 15:02 |
| ZipCPU | How about use the or1k-*-objdump -Dr <filename> ? (The * depends upon what compiler you have built.) | 15:18 |
| das | i'll try to install the toolchain and see what's what. thx | 15:20 |
| das | OTOH this at best will disassemble but won't help navigate the ASM code right? | 15:23 |
| das | like r2 would | 15:23 |
| ZipCPU | I'm not familiar with r2, and ... you asked for a tool to disassemble a project. | 15:23 |
| das | true | 15:26 |
| das | www.onlinedisassembler.com handles openrisc but it's not enough to help me reverse | 15:27 |
| ZipCPU | Reverse engineering is a time consuming and painful field of engineering. Be prepared to pay for whatever you wish to do in your own sweat. | 15:28 |
| das | ofc that's the point | 15:28 |
| das | I wouldn't need help for x86/arm | 15:29 |
| shorne | das: r2 is used as the frame pointer | 16:39 |
| shorne | there are good docs on it here | 16:39 |
| shorne | http://www.embecosm.com/appnotes/ean3/html/ch04s02s05.html | 16:39 |
| shorne | Also, you can get toolchains for linux here; https://github.com/openrisc/or1k-gcc/releases/tag/or1k-5.4.0-20170218 | 16:40 |
| shorne | just get or1k-elf-5.4.0... | 16:40 |
| shorne | stekern: is there anything from your mor1kx/multicore branch that is not upstream? | 16:52 |
| stekern | umm, I don't think so | 16:58 |
| shorne | stekern: I rebased the orpsoc-cores on latest, had to fix some things up in de0_nano-multicore | 17:53 |
| shorne | stuck it it on my de0_nano | 17:53 |
| shorne | and booted the kernel | 17:54 |
| shorne | it getst to here | 17:54 |
| shorne | smp: Bringing up secondary CPUs ... | 17:54 |
| shorne | CPU1: Booted secondary processor | 17:54 |
| shorne | CPU: OpenRISC-10 (revision 0) @50 MHz | 17:54 |
| shorne | so... almost there | 17:54 |
| shorne | its using the openrisc/mor1kx | 17:55 |
| --- Log closed Wed Mar 29 00:00:05 2017 | ||
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