IRC logs for #openrisc Thursday, 2017-03-02

--- Log opened Thu Mar 02 00:00:24 2017
mithrowallento: Any chance you'll get to look at my email about OpenDebugSoC?01:33
-!- karan__ is now known as karan12:49
shornewallento: stekern_: I have been looking at the SMP code in the kernel and usage of shadow regs.  Is this different from shadow regs in the SPEC?23:09
shornei.e. in the spec there is a way to check CPUCFGR for count of shadow regs.  But we dont do that in the kernel23:09
shornealso there is a SR[CID] we can enable to do context incrementing, but it seem we dont do that23:09
shorneor is the implementation all according to spec?23:12
stekern_shorne: the implementation should be spec-compliant23:13
stekern_but I can't remember all the gory details off teh top of my head23:13
stekern_we only use the shadow regs as scratch regs though23:14
-!- stekern_ is now known as stekern23:14
stekernwe're not using them *as* the actual registers ever23:15
stekernthe history in a nutshell is, we needed scratch reg to save state (since the hack with using the mem area around 0x0 doesn't work for smp), and I found that we could use the shadow regs without needing to do any spec changes23:17
shornestekern: ah, thanks that makes sense then as to why we are not using the "fast switching" stuff.  i.e. we never set SR[CE]23:26
shornewe are not using shadows for exception nesting, just for scratch23:26
shornethanks, clear now23:27
shornestekern: actually one question,  do you think it would make sense to remove the CONFIG_OPENRISC_HAVE_SHADOW_GPRS and replace with a check to CPUCFGR?23:32
shorneWe dont really want to do that at runtime for every save/load would need something tricky, like alternatives23:34
stekernyeah, I think that's why I went with the config option23:34
--- Log closed Fri Mar 03 00:00:25 2017

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