| --- Log opened Sat Jan 14 00:00:13 2017 | ||
| wbx | shorne: do you have a link to qemu patch? | 01:42 |
|---|---|---|
| shorne | wbx: haha, right you were working on qemu? here it is: | 03:05 |
| shorne | http://lists.nongnu.org/archive/html/qemu-devel/2017-01/msg02764.html | 03:05 |
| shorne | its pretty much a 3 line change | 03:05 |
| shorne | I am running my kernel here: https://github.com/stffrdhrn/linux/tree/openrisc-4.11 | 03:07 |
| shorne | but it should be the same as the openrisc/linux | 03:07 |
| shorne | mine is just behind a bit as I push the backlog of changes to upstream | 03:08 |
| shorne | well, I have some fixes for DSX handling too | 03:08 |
| shorne | I should push that change to openrisc/linux (will do after I submit for review to the list) | 03:08 |
| shorne | wallento: FYI, we were discussing the DSX (delay slot exception) code. my final patch is here: | 03:09 |
| shorne | https://github.com/stffrdhrn/linux/commit/2e0280d4461ede263eed586023c5e20f9abb6d97 | 03:09 |
| shorne | There were actually too issues here | 03:10 |
| stekern | shorne: so, the l.lwa/l.swa emulation works with those two patches? | 03:14 |
| stekern | btw, this isn't right https://github.com/stffrdhrn/linux/blob/openrisc-4.11/arch/openrisc/kernel/traps.c#L388 , is it? | 03:16 |
| stekern | that should be displacement, not register | 03:16 |
| stekern | same for l.bf | 03:16 |
| shorne | let me have a look, yes it boots after those patches | 03:37 |
| shorne | stekern: FYI, checkpatches https://gist.github.com/stffrdhrn/e911a7ca639adaebb81cc11065e6e072#file-openrisc-4-11-2016-jan-14-checkpatch-L68 | 03:38 |
| shorne | stekern: I thought the register will contain the address we want the pc to go to | 03:39 |
| shorne | regs->pc = regs->gpr[rb]; | 03:39 |
| shorne | let me see | 03:39 |
| shorne | EA ← exts(Immediate << 2) + BranchInsnAddr | 03:40 |
| shorne | PC ← EA if SR[F] set | 03:40 |
| shorne | you are right | 03:40 |
| shorne | yeah, not sure what I was thinking | 03:41 |
| shorne | good catch | 03:42 |
| shorne | ... As you said its hard to put a swa/lwa in a delay slot. So it has not really been tested yet | 03:42 |
| shorne | stekern: the kernel boots in qemu after just the qemu patch. The other patch will allow booting with DSX emulation is turned off. | 03:46 |
| shorne | (I think the entry patch will fix all targets, not just qemu) | 03:46 |
| shorne | :: pushed fixes to git (rebased) :: | 04:05 |
| stekern | yeah, you probably have to do a dedicated test that puts them in the delay slot to test that code | 04:34 |
| mor1kx | [mor1kx] bandvig pushed 1 new commit to marocchino_devel: https://github.com/openrisc/mor1kx/commit/a54f8e2aaba04354266cb2576bbcca0bf5a266a5 | 09:44 |
| mor1kx | mor1kx/marocchino_devel a54f8e2 Andrey Bacherov: Major modification is speculative write back for LSU. Find more details in marocchino_2_status_plans.txt | 09:44 |
| shorne | ok, patches sent | 18:11 |
| shorne | for review | 18:11 |
| ZipCPU|Laptop | I have a question for all you OpenRISC users/developers out there ... how do you get the initial ram/boot image onto the CPU? | 21:59 |
| ZipCPU|Laptop | Sure, you can start from flash ... but you still need to get that initial flash image up, right? | 21:59 |
| ZipCPU|Laptop | adv_debug_sys? | 21:59 |
| ZipCPU|Laptop | jtag_tap? | 22:00 |
| ZipCPU|Laptop | Or does OpenRISC use a separate booting protocol? | 22:00 |
| --- Log closed Sun Jan 15 00:00:15 2017 | ||
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