IRC logs for #openrisc Saturday, 2017-01-14

--- Log opened Sat Jan 14 00:00:13 2017
wbxshorne: do you have a link to qemu patch?01:42
shornewbx: haha, right you were working on qemu? here it is:03:05
shorneits pretty much a 3 line change03:05
shorneI am running my kernel here:
shornebut it should be the same as the openrisc/linux03:07
shornemine is just behind a bit as I push the backlog of changes to upstream03:08
shornewell, I have some fixes for DSX handling too03:08
shorneI should push that change to openrisc/linux (will do after I submit for review to the list)03:08
shornewallento: FYI, we were discussing the DSX (delay slot exception) code.  my final patch is here:03:09
shorneThere were actually too issues here03:10
stekernshorne: so, the l.lwa/l.swa emulation works with those two patches?03:14
stekernbtw, this isn't right , is it?03:16
stekernthat should be displacement, not register03:16
stekernsame for l.bf03:16
shornelet me have a look, yes it boots after those patches03:37
shornestekern: FYI, checkpatches
shornestekern: I thought the register will contain the address we want the pc to go to03:39
shorneregs->pc = regs->gpr[rb];03:39
shornelet me see03:39
shorneEA ← exts(Immediate << 2) + BranchInsnAddr03:40
shornePC ← EA if SR[F] set03:40
shorneyou are right03:40
shorneyeah, not sure what I was thinking03:41
shornegood catch03:42
shorne... As you said its hard to put a swa/lwa in a delay slot.  So it has not really been tested yet03:42
shornestekern: the kernel boots in qemu after just the qemu patch.  The other patch will allow booting with DSX emulation is turned off.03:46
shorne(I think the entry patch will fix all targets, not just qemu)03:46
shorne:: pushed fixes to git (rebased) ::04:05
stekernyeah, you probably have to do a dedicated test that puts them in the delay slot to test that code04:34
mor1kx[mor1kx] bandvig pushed 1 new commit to marocchino_devel:
mor1kxmor1kx/marocchino_devel a54f8e2 Andrey Bacherov: Major modification is speculative write back for LSU. Find more details in marocchino_2_status_plans.txt09:44
shorneok, patches sent18:11
shornefor review18:11
ZipCPU|LaptopI have a question for all you OpenRISC users/developers out there ... how do you get the initial ram/boot image onto the CPU?21:59
ZipCPU|LaptopSure, you can start from flash ... but you still need to get that initial flash image up, right?21:59
ZipCPU|LaptopOr does OpenRISC use a separate booting protocol?22:00
--- Log closed Sun Jan 15 00:00:15 2017

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