IRC logs for #openrisc Sunday, 2017-01-15

--- Log opened Sun Jan 15 00:00:15 2017
-!- shorne_ is now known as shorne02:55
shorneZipCPU: I think its adv_debug_sys, but you can see in the fusesoc-cores repo how each soc is configured02:56
shornebasically for most "bootstrapping" its OpenOCD --> jtag --> target02:57
shorneAlso you can store a bootloader into flash which the cpu can boot from, I havent tried that yet, but olofk was talking about that recently.02:59
shorneHello, wallento, stekern: I did a pr for musl cross version bump here03:39
shorneIf no issue I would like to merge03:39
wallentoYes, please merge03:41
promachhi, I am trying to have a build of mor1kx on my FPGA board. I just have a UART softcore running. How would I proceed ?03:41
shornewallento: thanks, will do after travis passes03:42
shorneI should make a news announcement and post to the website like you did before too03:42
shorneI am not so good at that though03:42
wallentoyou are right, that is a great idea03:50
wallentoplease do, I am sure it will be good :)03:51
bandvigZipCPU: I use U-Boot on my Atlys board. I upload prepared U-Boot image by Ethernet with TFTP.05:28
promachI am having problem06:30
promachpkg_resources.DistributionNotFound: The 'fusesoc==1.5' distribution was not found and is required by the application06:30
promachI have fusesoc installed in a virtualenv06:31
promachwith this command env/bin/pip install fusesoc06:31
promachpython -m venv env06:32
ZipCPU|Laptoppromach: Olof usually answers any fusesoc issues, but I don't see him on the users list for this channel.07:41
ZipCPU|Laptopbandvig, shorne: Thanks for your answers!07:42
ZipCPU|LaptopI certainly found adv_debug_sys connected to all the systems I examined within the orpsoc-cores set.07:43
ZipCPU|Laptopbandvig: uboot ... sure, but ... how do you get uboot on your board? That's really my question--how you get the first, virgin load, onto your FPGA board.07:44
bandvigZipCPU|Laptop: it was really quite long story. Some times ago I told it here. Shortly speaking I followed in my OpenRISC journey08:09
ZipCPU|Laptop"The official implementation [of OpenRISC] is maintained by developers at" ... still?  ;P08:14
ZipCPU|LaptopThat was a lot of reading just to learn that you used the IMPACT tools to load your first program into flash and then ran from there.08:29
promacholofk: I have a problem with fusesoc10:28
promach<promach> pkg_resources.DistributionNotFound: The 'fusesoc==1.5' distribution was not found and is required by the application10:29
promach<promach> with10:29
promach<promach> I have fusesoc installed in a virtualenv10:29
promach<promach> with this command env/bin/pip install fusesoc10:29
promach<promach> and10:29
promach<promach> python -m venv env10:29
mafmis there any openrisc presence at fosdem?16:39
olofkmafm: Not sure actually.16:47
olofkwallento: You're going to FOSDEM?16:47
olofkSeems like I missed quite some discussion while I was busy rebuilding the network at home16:48
olofkNetwork over the power lines is great btw! As long as you find some good outlets to plug in the stuff16:48
olofkZipCPU: By default, an OpenRISC CPU is set up to run from address 0x10016:49
olofkWhat we normally do however, is to make it start executing from address 0xf0000000 (just a convention), where we have placed a boot ROM16:49
olofkWith FuseSoC it's of course easy to select which ROM contents you want to use16:50
olofkThe two most widely bootloaders (to be placed in that ROM) is16:50
olofk1. Clear r3 and jump to address 0x100. This is good when you are using a JTAG debugger and adv_debug_sys to program an application to RAM16:51
olofk2. Load an image from SPI Flash and jump to address 0x10016:51
olofkI've been considering several other bootloaders as well16:51
mafmolofk: I didn't find any talk scheduled by the name of "openrisc" or "or1k", but there might be many topics related to openrisc/librecores, so just asking16:52
olofkSuch as listen to a UART, where it could accept a file in Intel/Motorola hex format that could be programmed to RAM16:52
olofkOr a zmodem receiver16:52
olofkmafm: Yes, there will be presence from FOSSi Foundation. I'd love to go myself, but I can't this year16:53
olofkThe hardest part of writing these boot loaders has been that I can't use any RAM, since I don't know if the application will overwrite it, so I'm writing them in 100% asm to make sure that they only use registers for storage16:54
mafmolofk: btw, there are good chances that I will attend orconf 2017 if it's in the UK :D16:59
mafmtoo bad that riscv conf is in china, no way to go there :(16:59
olofkmafm: Great. Looking forward to see you again at orconf17:01
mafmolofk: is there any proposal about where in the UK it would be?17:10
olofkmafm: Yes. We will announce it later this month17:11
mafmhope that it's close to Stansted :D17:15
mafm(Cambridge or London, that is :P)17:16
shornemafm: riscv in china? Im in Japan, maybe I can swing by :)17:20
andrzejrshorne, where in Japan are you?17:33
mafmshorne: I think that in shanghai, but not officially announced yet17:36
shorneandrzejr: tokyo17:39
andrzejrshorne, I've been living there myself for some years. Tokyo, Yokohama.17:43
olofkstekern: I'm considering to remove the qsys stuff you added for the quartus backend in FuseSoC. The code is becoming a bit hard to maintain, and I think it could be done by a tcl script that is launched by FuseSoC instead. Any thoughts?18:06
promacholofk: did you see my question ?18:54
stekernolofk: sure, that's probably doable23:35
--- Log closed Mon Jan 16 00:00:16 2017

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