IRC logs for #openrisc Thursday, 2016-12-08

--- Log opened Thu Dec 08 00:00:17 2016
shorne_franck_: that is what I am thinking "not only solution" im looking at other examples for something02:31
olofk__franck_: Seems to work! Awesome, thanks02:53
promachhow to implement openRISC on Parallella ? Do I need to port mor1kx to Parallella ? and also I found that Parallella Zynq PS has control to almost all the peripherals03:16
promachanyone have any advise ? is Parallella platform good for softcore CPU development ?03:16
olofk_promach: I wouldn't say that Parallella is particularly suited for doing softcore development03:26
olofk_OTOH, eliask, ported a RISC-V CPU to Parallella as a GSoC project this year03:26
promachyes, I saw that too. A rocket RISC-V core03:27
olofk_I suck at C. Am I supposed to use open or fopen to open files? :)03:56
shorneolofk_: it matters if you want to do fread or read :)04:02
shorne'f' one gives you a FILE plain one gives you an int file descriptor04:02
shorneif you want buffers and caches handled for you use 'f' functions04:04
shorneyou probably know all of that04:04
LoneTecholofk_: open is low level posix, fopen is C standard library04:36
olofk_Seems like the f family is the right choice for me then. Just want to do simple reads and writes05:43
-!- olofk_ is now known as olofk05:45
promach    upstream or development sources ?21:42
promach how many FPGA LUT resources would this multicore LUT will take approximately ?22:09
shornepromach: all building should currently be done with the openrisc/ repo sources in my opnion23:09
shornenewlib has a few patch missing upstream23:10
shornegcc is not upstream23:10
shornebinutils-gdb has a lot pending upstream23:10
--- Log closed Fri Dec 09 00:00:19 2016

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