IRC logs for #openrisc Thursday, 2016-11-24

--- Log opened Thu Nov 24 00:00:57 2016
olofkjuliusb: fusesoc build atlys02:33
olofkThat just builds the FPGA image though. There isn't any good way to also build the drivers and stuff from orpsocv202:35
olofkAnd the FPGA generation randomly fails because of some P&R bug in ISE that fails to place a clock buffer. People have been reporting this for years and we have moved that damn buffer back and forth02:36
olofkI only encountered it myself for the first time a few days ago, so yeah, it's pretty random02:36
olofkOther than that, it works fine, even if the Atlys port should get some more love when it comes to wishbone arbitration and bootloader02:36
arand___olofk: Hmm, to my (asm-inexperienced) eyes that does definitely look like it iterates through only the cache, in block steps.   Thanks.03:19
arand___So this would mean that if I want to invalidate the data cache for a read buffer that is 64K (e.g. post-DMA), I only ever need to invalidate max 8K? And can do so by invalidating on the addresses 0x0, 0x10, .., 0x1FF0?08:34
@juliusbolofk: awesome thanks18:09
--- Log closed Fri Nov 25 00:00:58 2016

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