| --- Log opened Thu Nov 24 00:00:57 2016 | ||
| olofk | juliusb: fusesoc build atlys | 02:33 |
|---|---|---|
| olofk | That just builds the FPGA image though. There isn't any good way to also build the drivers and stuff from orpsocv2 | 02:35 |
| olofk | And the FPGA generation randomly fails because of some P&R bug in ISE that fails to place a clock buffer. People have been reporting this for years and we have moved that damn buffer back and forth | 02:36 |
| olofk | I only encountered it myself for the first time a few days ago, so yeah, it's pretty random | 02:36 |
| olofk | Other than that, it works fine, even if the Atlys port should get some more love when it comes to wishbone arbitration and bootloader | 02:36 |
| arand___ | olofk: Hmm, to my (asm-inexperienced) eyes that does definitely look like it iterates through only the cache, in block steps. Thanks. | 03:19 |
| arand___ | So this would mean that if I want to invalidate the data cache for a read buffer that is 64K (e.g. post-DMA), I only ever need to invalidate max 8K? And can do so by invalidating on the addresses 0x0, 0x10, .., 0x1FF0? | 08:34 |
| @juliusb | olofk: awesome thanks | 18:09 |
| --- Log closed Fri Nov 25 00:00:58 2016 | ||
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