IRC logs for #openrisc Sunday, 2016-10-02

--- Log opened Sun Oct 02 00:00:38 2016
kc5tjaOnly two instruction classes remain to be implemented: conditional branches and SYSTEM instructions.00:09
-!- impihl is now known as imphil08:26 seems back, but media wiki gone?
shorneopenrisc ABI spec mentions "Structure and union arguments are passed as pointers."10:00
shorneDoes anyone know any other ABI's that do this? It seems all others pass all data on the stack10:01
shorneI mean regs then stack10:01
wallento_I roughly remember this was an issue before (specifically the difference between varargs and standard args)10:17
Laksenshorne, maybe Linux-PowerPC ABI10:18
shorneLaksen: thanks, Ill have a look10:33
shornewallento_: yeah, I am just wanting to discuss in my orconf presentation about ABI strangeness and wanted to mention this as something that causes issues10:34
shornerelated to my gdb work10:34
wallento_we even had a vote three years ago at orconf10:49
wallento_and the "don't break ABI compliance" won over the "but the others do it and some crappy code makes stupid assumptioms" won10:49
wallento_I think it was xfw or so casting variadic to non-variadic function pointers10:50
wallento_which crashed on OpenRISC10:50
wallento_but stekern knows better, he had the headache back then IIRC10:50
kc5tjaHoly **CRAP** is WAY faster than I remember it being now.  :)  Pleasant surprise this morning.11:53
ZipCPUkc5tja: I'm wondering if open cores isn't being hosted on github now as a server, since once when they were15:12
ZipCPUsetting up, I got a github error message.15:12
kc5tjaI never knew they were hosted on Github.  Seems like much too dynamic a site to be hosted there.16:33
kc5tjaOMG.  I've reached a milestone.  An epic milestone.16:33
kc5tjaPolaris Verilog is now ready to receive interrupt and trap support.16:33
--- Log closed Mon Oct 03 00:00:39 2016

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