| --- Log opened Mon Oct 03 00:00:39 2016 | ||
| kc5tja | ZipCPU: olofk: I know you folks have expressed an interest, so here's a bit of a status update: https://hackaday.io/project/10035-kestrel-computer-project | 11:10 |
|---|---|---|
| olofk | kc5tja: Thanks. Always interesting to read about your progress | 15:24 |
| ZipCPU | kc5tja: A fascinating update. Did I ever tell you that I initially tried to implement traps using an external register? I was going to keep the CPU simple--if you needed a trap, you just wrote the trap address to the external register, and it would interrupt the CPU. | 16:08 |
| ZipCPU | The interrupt handler (supervisor mode) could then check the trap ID and know what the user wanted. | 16:08 |
| ZipCPU | I had to abandon this approach due to timing: It would take about 2-3 cycles for the trap to interrupt the CPU following the instruction that wrote to the trap register. | 16:08 |
| ZipCPU | This ... just didn't pass the smell test for me. | 16:08 |
| ZipCPU | In other words ... watch out for the timing gotcha's with your CSR as external registers approach. | 16:09 |
| kc5tja | Yeah, Polaris has to have a mechanism to handle traps built-in. That much is certain. | 17:51 |
| kc5tja | However, that relates more to the "something has happened" event notification logic itself, and not so much to the processor state management. | 17:53 |
| --- Log closed Tue Oct 04 00:00:41 2016 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!