IRC logs for #openrisc Monday, 2016-10-03

--- Log opened Mon Oct 03 00:00:39 2016
kc5tjaZipCPU: olofk: I know you folks have expressed an interest, so here's a bit of a status update:
olofkkc5tja: Thanks. Always interesting to read about your progress15:24
ZipCPUkc5tja: A fascinating update.  Did I ever tell you that I initially tried to implement traps using an external register?  I was going to keep the CPU simple--if you needed a trap, you just wrote the trap address to the external register, and it would interrupt the CPU.16:08
ZipCPUThe interrupt handler (supervisor mode) could then check the trap ID and know what the user wanted.16:08
ZipCPUI had to abandon this approach due to timing: It would take about 2-3 cycles for the trap to interrupt the CPU following the instruction that wrote to the trap register.16:08
ZipCPUThis ... just didn't pass the smell test for me.16:08
ZipCPUIn other words ... watch out for the timing gotcha's with your CSR as external registers approach.16:09
kc5tjaYeah, Polaris has to have a mechanism to handle traps built-in.  That much is certain.17:51
kc5tjaHowever, that relates more to the "something has happened" event notification logic itself, and not so much to the processor state management.17:53
--- Log closed Tue Oct 04 00:00:41 2016

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