IRC logs for #openrisc Friday, 2016-09-16

--- Log opened Fri Sep 16 00:00:14 2016
olofkAnyone got experience with doing FFT in FPGAs?01:55
-!- knz_ is now known as knz06:07
ZipCPU|Laptopolofk: Yes.06:57
ZipCPU|LaptopI built an open core FFT builder some time ago.06:57
ZipCPU|LaptopIt's a C++ program that builds the Verilog necessary to accomplish your FPGA.06:58
ZipCPU|LaptopIt's designed to handle two samples per clock, but it shouldn't be too hard to modify if you have other needs.06:58
ZipCPU|LaptopI've also got code lying around to do perform a high resolution FFT as well.07:00
olofkZipCPU|Laptop: Cool. Want to share?07:01
olofkAnd what's the interface? Do you stream in the samples, or are they fetched from a memory?07:02
ZipCPU|LaptopThe open core FFT builder builds a core that streams in two samples at a time, together with a CE signal.07:02
ZipCPU|LaptopThe CE signal is used to gate the core to whatever speed you are actually running at, although it uses the amount of fabric it would need to run at full speed.07:03
ZipCPU|LaptopThe output is similar: when the input CE is high, there's a valid pair of samples on the output.07:03
ZipCPU|LaptopThe only trick is the first sample.07:04
shornestekern: If you have no objection, I am going to send this patchset to the kernel list looking for help getting it merged
ZipCPU|LaptopOn the first sample of the output, the core also strobes a wire, so you know how to line yourself up.07:04
shorneI just put Rob Herring's recent patch on as a bonus07:04
shorneI tested and it all seems ok07:04
stekernshorne: LGTM, but you should squash "openrisc: copy thread pointer from userregs" and "openrisc: Add thread-local storage (TLS) support" together into one patch07:06
stekern(i.e. just update Christian's change with the change in the latter)07:07
shornecool, no problem...07:09
shorneI squashed and kept blueCmd's original commit message, added you as signed off by if thats ok07:17
shorneI push forced the changes to here :
ZipCPU|Laptopolofk: I should also point out, the core is *quite* configurable.  You pick the FFT size, whether forward or inverse.  You pick the input and output sample width, together with the coefficient size and the internal sample widths, etc.  Defaults are provided for anything you don't configure.07:20
ZipCPU|LaptopOh, and you can also pick the number of hardware multiplies you have available.  It will use up to that number, and then do multiplies in fabric afterwards.  (Fabric muliplies are quite painful, though.)07:21
blueCmdshorne: that's fine by me07:21
olofkZipCPU|Laptop: Regarding hw multipliers, do you target Cyclone IV primitives?07:24
shorneblueCmd: thanks for acking07:25
ZipCPUolofk: I've only tested the core with Xilinx hardware.07:27
ZipCPUWould you like to test it on Altera and help me improve the core?07:27
ZipCPUThe core depends upon the multiplies being inferred.07:28
olofkAre not the fabric multiplers inferred too? Or do you have a hand-written implementation for those?07:31
ZipCPUThe fabric multipliers are hand-written.07:32
ZipCPUI had to guarantee a known timing, and for an arbitrary width ... hence the hand-written implementation.07:32
olofkYeah, I need an FFT, and as I have an excellent support person for this one, I'm happy to try it out :)07:33
ZipCPUIf two samples per clock is overkill for what you need, it shouldn't be too hard to modify the core for a single sample per clock.  I just haven't done it (yet).07:34
blueCmdshorne: thanks for taking care of things :)07:34
olofkblueCmd: Are you coming to orconf this year?07:35
blueCmdolofk: nope, too many other things going on in my life currently07:39
blueCmdolofk: moving and switching work07:39
olofkAha. Changing employer, or just updating your location again?07:40
blueCmdi do look at my FPGA board from time to time and it would be fun to pick up some kind of project07:40
blueCmdolofk: employer07:40
olofkblueCmd: Yeah. I do that too. With my eight FPGA boards just collecting dust :(07:40
blueCmdolofk: moving to el Stockholmo and joining a small app company07:40
olofkaha. Interesting07:40
olofkIf you're there on 13 October, I will do a breakfast seminar on Open Source Silicon07:41
olofkWe are announcing it on monday :)07:41
blueCmdI am, it's like 3 days after I start :P07:41
_franck__FYI, lot of cool stuff here:
olofk_franck_: I think he's been trying to do a webserver in HDL :)07:48
olofkSeen him on tiwtter07:49
shorneolofk: he needs fusesoc07:49
olofkshorne: They all do :)07:49
_franck__this display port stuff is quite cool07:49
_franck__I was thinking doing one07:50
olofkAnd I need more people to create packages. Been writing a ton of cores07:50
ZipCPU|Laptopolofk: What do you mean by needing more people to create packages.  How are packages different from cores?  Are these the "systems" within orpsoc-cores that you are referencing?08:39
olofkI mean .core files08:45
ZipCPU|LaptopYou mean ... like if I just added .core files to all my cores, then they'd be more useful?08:45
olofkI've done most of the cores in the FuseSoC standard library myself. It's not that hard, but it takes a while for each of them08:46
olofkYes. That is what I mean. The point is to make them easier to integrate in other projects08:46
ZipCPU|LaptopOk.  Got it.08:46
shornestekern: ok, I sent a mail explaining the situation, hopefully I dont get too badly burt for sending spam10:53
shorneSo, those patches to the kernel list have 2 issues (I hsould have found myself)18:07
shornepatch 3/7 needs to have the comment fixed up18:08
shornepatch 1/7 breaks non openrisc builds18:09
shorneIll fix both18:09
--- Log closed Sat Sep 17 00:00:15 2016

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