IRC logs for #openrisc Thursday, 2016-09-15

--- Log opened Thu Sep 15 00:00:12 2016
-!- heroux_ is now known as heroux04:24
shornestekern: Now I have the fixes reshared as per this link08:12
shorne*reshaped*, sqaushed the or32 toolchain fix, and removed dts for now08:13
shornebut, I think having the dts in tree does 2 things, makes build easier + makes our support for hardware much better advertised08:19
shorneBut I do agree that autogenerating dts by something like looking at wb config in fusesoc would be awesome08:20
olofkshorne: Yeah. I'm fine with having them in the tree. Just that it doesn't scale very well with many different boards and configurations08:22
olofkWe still haven't defined some kind of baseline functionality, which would have helped08:22
olofke.g. 32MB RAM, UART@0x90000000, GPIO@0x91000000, SPI@0xB000000008:23
shorneyeah, but have a look at
shornebut I think we can do better :)08:24
SMDhomeshorne: what's wrong w/ having tons of dts files in kernel dir?08:25
shorneSMDhome: I am ok with it, but since our hardware is open, we have both the SOC config in source and dts in source08:26
shornethey are virtually equivelent it might be nice to generate dts from the source soc (verilog, wb bus config) source08:27
shorneBut then again, the kernel driver names etc would be hard to map to08:29
shorneand keep in sync with the kernel, I think keeping out of tree we would not be able to keep up to date with api changes/ refactoring etc08:30
SMDhomeshorne: and what if you make some preconfigured SoCs(i.e. for de nano and digilent board) and dts for them? And for enthusiasts there will be generic dts with guide or generator to configure dts08:34
olofkSMDhome: I've been encouraging people to put dts files in the top-level FuseSoC cores08:48
olofkWe got for atlys and neek so far08:49
SMDhomeolofk: do  you have a board w/ mor1kx in it now? Could you run a binary there just for test?08:52
olofkSMDhome: You could, but it would be awkward08:53
olofkBut I have been running a system quite recently with just mor1kx+block RAM+JTAG08:54
SMDhomeolofk: I'm trying to run coremark, but it takes too long even on verilator08:54
olofkah ok08:55
SMDhomeSo I'd like to know if that tests ever ends :)08:55
olofkHow much RAM does it need?08:55
olofkRunning it on a de0_nano or similar would probably be pretty simple08:57
olofkYou need CPU+RAM at least. And it's probably nice to have a UART to watch the output08:57
SMDhomethat's a good question! Last addr in binary disasm is 0x13cfc08:57
olofkAnd JTAG for loading the program at runtime08:57
SMDhomeshould I get de0-nano dev & educational board instead of de0-nano-soc? Seems like the latter has no ram connected to the fpga10:26
--- Log closed Fri Sep 16 00:00:14 2016

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