IRC logs for #openrisc Wednesday, 2016-08-03

--- Log opened Wed Aug 03 00:00:08 2016
* mafm dislikes pages like OpenPiton's05:56
mafmbut they are everywhere now05:56
ZipCPUmafm:What's wrong with OpenPiton's page?09:44
mafmZipCPU: I don't like the general style of these newfangled pages!  now get off my lawn, etc :P :D10:16
kc5tjaThe fact that you have to scroll on a 1600-pixel tall display is pretty damn loathesome.10:57
kc5tjaJust to see the slightest bit of information about the project.10:57
kc5tjaThat color scheme is pretty garish too.10:58
kc5tjaReminds me vaguely of AmigaOS 1.2, with its blue background and nightmare-inducing-orange color for highlights.10:59
kc5tjaWhat really burns me up are the webpages that have parallax scrolling.11:02
kc5tjaI suffer from vertigo, and those pages are very disorienting to me.11:03
kc5tja(at least if the effect is very pronounced.)11:03
ZipCPUWell ... I'm making progress.  I discovered that I hadn't turned the DLL on.  Now that the DLL is on, the bits are making more sense.14:37
ZipCPUStill, if I write a bunch of ones, they turn into zeros over time.  I wonder if that's a refresh bug?14:37
ZipCPU(Working with a DDR3 SDRAM ...)14:38
kc5tja^--- That, THAT, right there, is why I opted to not go with SDRAM as my first-generation online memory system for the Kestrel.  Because I knew stuff like this would inevitably happen.  ;)15:53
ZipCPUkc5tja: If you're not failing, you are not trying hard enough.  :P15:53
kc5tjaOh believe me, I'm EPICALLY failing right now, even w/out the SDRAM complexity.  :D15:54
kc5tjaSo far, I have instruction decode for OP-IMM and OP-IMM-32 instructions working.  Still haven't had the time to implement LOAD or STORE instruction classes yet.  :(15:55
-!- sandeepkr is now known as X7R15:57
ZipCPU|LaptopWell, that's a good start ....15:58
kc5tjaI get these days of extreme productivity, and then week-long spans of procrastination.16:01
-!- X7R is now known as sandeep16:21
-!- sandeep is now known as sandeepkr16:21
Findekc5tja: I feel the same about the page16:57
Findeunfortunately as I wasn't willing to make a page myself, I just have to put up with it16:57
mafmFinde: are you from that project?  didn't mean to offend :D17:06
mafmthis kind of design seems to be popular in many places, e.g. the Jolla phone company17:07
kc5tjaI'm so confused.  Which project?17:07
mafmkc5tja: I am guessing that the openpiton page that we were talking about before, but maybe I am wrong17:08
olofkCould someone give me a name for a cheap USB JTAG adapter?17:08
kc5tjamafm: Ahh, about the website design.  Well, better to have actual silicon working than a nice pretty website without any content at all.17:09
olofkDon't underestimate the power of a nice website. The complete mess of the different sites traditionally used for OpenRISC have turned away more than a few poeple who thought it was just something old and forgotten17:16
* kc5tja nods17:17
kc5tjaThat's the single biggest fear I have with the Kestrel websites.17:17
kc5tjaThe Kestrel site is pretty austere and monochrome, which is nice for having a fast-loading page.17:18
kc5tjaBut, it's not at all "professional."  Very HTML 1.0.17:18
olofkkc5tja: I must say that Kestrel has better web resources than most projects I have seen17:18
olofkkc5tja: Have you for example seen the FuseSoC homepage?17:22
ZipCPUolofk: Is there a FuseSoC homepage?17:28
olofkZipCPU: Nope. That was my point :)17:29
ZipCPUolofk: Point made.17:30
olofkI did buy several years ago though. Just haven't taken the time to put up something17:30
olofkThinking of just publishing my poster from the RISC-V workshop there since it probably contains more info than any other source17:30
Findehaha mafm yeah I'm the lead author on the ASPLOS paper about the chip17:47
FindeI mean the platform17:47
Findebut yeah I agree about the site17:47
mafmFinde: so it's ready to tape out, according to the site?17:57
Findewe have silicon in the lab17:57
FindeMike's giving a talk at hotchips at the end of the month17:57
Findesee day 2:
Findethe videos usually get uploaded after too17:58
mafmFinde: will the lab tape out / sell commercially, or a spin-off, or no reals plans yet?17:59
mafm(btw, it's a sparc32 or a sparc64?  Debian removed the former)17:59
Findewe're happy to share with collaborators but we're not planning on selling it as a product17:59
mafmah, nice :)18:00
Findeunfortunately a 6x6mm chip in IBM 32nm is a bit expensive18:00
Findeit's mainly a way of testing out some research ideas we had18:00
mafmI always wondered why people didn't try to do anything with opensparc... I blamed it on Oracle/Ellison18:00
Findehence us then releasing openpiton for other researchers to use18:00
Findeyeah me too18:00
mafmFinde: I'm totally oblivious to the perils of fabrication processes and so on, but do you think that it would possible/easy to have it in low volumes as cpu-card in ?18:03
mafmor it's only possible with some arm chips because the fabrication plans already have the chips?18:04
ssvbmafm: I think the RISC-V people were talking about something like $30K per test batch, I guess one may expect a few failed attempts before something useful is produced, but this does not look like something that is totally beyond a crowdfunding budget18:13
ssvbmafm: (around 45:00)18:14
ssvbmafm: also and various bitcoin miner startup companies managed to arrange manufacturing of their own ASIC chips, so this seems to work in practice18:16
ssvbFinde: 6x6mm seems like a relatively big chip18:18
mafmssvb: so according to what you and Finde say, the openpiton needs to go through the testing batches first?18:20
ssvbmafm: don't pay much attention to what I say, I don't have first hand information and just found it on the Internets :-)18:22
mafmssvb: olofk also said that openrisc would not be ready for such cpu-cards because it needs to be made ready for ASIC, tested and so on, so I suppose that all of these have their problems18:24
mafmbefore being "mass"-produced18:24
mafmsince opensparc was a commercial effort before, and tape-out is mentioned in openpitor, I was wondering if they were a bit further ahead :)18:25
ssvbmafm: the RISC-V people seem to claim that their designs are already ASIC proven, and I'm looking forward to what is eventually going to offer (they need a whole SoC, not just a CPU alone)18:30
mafmssvb: yeah, I'm also looking forward to that, but let's see :)18:40
kc5tjaWhat's funny re: OpenSPARC is that SPARC is essentially RISC-I.  :)  (I believe it's based on the RISC-I architecture.)18:49
kc5tjaRISC-V is definitely ASIC proven; however, the ASICs were student projects, and not released to the public.  SiFive is probably the closest at this point to getting workable, commercially available silicon out the door.18:50
kc5tjaBut even then, they're catering towards custom silicon.18:50
mafmyeah, agree with kc5tja19:02
kc5tjaSometimes, I question whether or not I should have gone with RISC-V for Kestrel-3.  A MISC architecture CPU (for example, a CPU optimized to run Forth) would have been substantially simpler to design and go with in retrospect.19:04
kc5tjaI should have stuck to my guns.19:05
kc5tjaThe opportunities RISC-V offered (and still offers) is very appealing, though.19:06
mafmkc5tja: yeah, but things are coming sooooooo much slower than I expected... and I think that I'm not the only one....19:07
mafmwell, time to go to bed for me, night!19:20
* ZipCPU|Laptop just looked chat commands21:44
--- Log closed Thu Aug 04 00:00:09 2016

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