IRC logs for #openrisc Tuesday, 2016-08-02

--- Log opened Tue Aug 02 00:00:06 2016
stekernolofk: btw, I suspect omega2 has a MIPS cpu. I can't find anywhere actually saying it, but the omega predecessor had MIPS04:50
stekern...which in some sense make it more fun than "just another arm board"04:51
olofkZipCPU: Do you use the DFI interface between the controller and phy? If not, I would recommend doing that, as I think this standard is quite useful16:35
ZipCPUolofk: Looking it up now ...16:36
olofkI know that _florent_ has implemented some DFI phys, so there might even be a possibility to reuse them16:37
ZipCPUHmm ... from Xilinx's forums, "No, there is no way to generate a DFI interface for the 7 Series MIG design.  You might be able to create some sort of shim or pay someone to do it for you, but it isn't currently available from Xilinx."16:38
ZipCPUSo ... I guess my answer is that no, I did not use it.16:38
ZipCPUHowever, with what I've been going through today ... I might've appreciated using it ;)16:39
ZipCPUToday's work has been trying to get the controller working on the hardware.  I have a simple test script of reading and writing values.16:39
ZipCPUThere are only 8 test values, but I'm not getting back what I'm writing (yet).16:39
ZipCPUWhat I wouldn't give for a good scope at this time ... something good enough to give me 4-8 samples per clock on each pin.16:40
olofkZipCPU: Yeah. I almost lost my mind with my ddr2 controller. After getting it working in simulations, I never managed to get it working on real hw16:56
ZipCPUNever got it to work?16:57
ZipCPUAny idea why not?16:57
olofkTiming probably16:57
ZipCPUYou're guessing in the dark.  ;)16:57
olofkDefinitely :)16:57
olofkBut DFI is a great abstraction, since it separates the (possibly) technology-independent controller from the very tech-specific phy16:58
ZipCPUI don't believe in voodoo computers.  There's always a cause that can be determined.  It's just a matter of figuring out what and how.16:58
ZipCPUYeah, sure, if only I could use it.  Sigh.16:58
olofkYes, but I was running way behind on that project. I was at a point where I was ready to give up. In the end it turned out that I was given the wrong pinout too, and I finally settled for Altera's DDR2 controller with a wb-avalon bridge that _franck_ had written for this exact purpose16:59
olofkI still would like to finish this though, as I had some good ideas how to make the cores more modular17:00
ZipCPUWrong pinout, huh?  That's about the only thing that will explain what I'm seeing, and yet I've already gone back and verified the pinout with two different vendor supplied sources.17:00
ZipCPUI'm providing the core with some really simple commands.  The timing on the commands should be simple: one command per clock.17:01
olofkZipCPU: I wish I could help you more, but DDR interfaces are hard17:01
ZipCPUAfter the commands, I'm setting the data to a string of all zeros or all ones.  Timing in the middle of the string shouldn't be a problem--nothing's changing.17:01
olofkMy idea was (and still is) to use stekern's wb_sdram_ctrl, but split it up into three parts17:01
olofk1. A phy with a DFI interface17:02
olofk2. A controller that can be configured for SDRAM/DDR2/DDR317:02
olofk3. A multi-port wishbone slave with coherent cached ports17:02
olofkI even invented a new bus interface to connect between 2 and 3 :)17:03
ZipCPU(I did manage the SDRAM controller ... that wasn't too hard.)17:03
ZipCPUReally ... what did your bus interface look like?17:03
olofkI called it CAMD17:04
olofkIt was similar to Xilinx (badly documented) UI interface17:04
olofkOne port provides Address and command (read or write)17:04
olofkOne port provides data and mask17:04
olofkOne port provides return data17:04
olofkAll three ports have a valid/ready handshaking, a la AXI417:05
ZipCPUI've been chatting w/ Rob Finch [sp] about that sort of thing on OpenCores/forum already.  My (unsaid) proposal would be to use WB to do that.17:05
olofkI've seen the discussion. Been meaning to reply, but haven't had time17:06
ZipCPUHe'd like a 128-bit DDR3 controller with 8 ports, running at 50MHz.  I figure that could easily drive, via wishbone, the controller I have: a 32-bit controller at 200MHz.17:06
ZipCPUDo you have insights you'd like to share?  If so, do please join the discussion!17:06
olofkWell, wb_sdram_ctrl contains the logic for the multiport stuff. Each port also has a small cache, so that it will always do full acceses to the RAM even if we only request a single word17:07
ZipCPUSo ... you believe much of Rob Finch's work is already done?17:08
olofkIt frustrates me to no end that I never was able to finish my work after all the time I spent on that17:09
ZipCPUI can relate to that.17:10
ZipCPUolofk: Do you think the bad pin out was a simple error, or a conspiratorial design to keep you from doing this?17:22
ZipCPUI'm leaning towards the latter ...17:23
olofkok, answered now17:24
olofkZipCPU: Oh no. My client had just given me outdated schematics. Everyone was panicking since I wasn't making any progress17:25
olofkI was going to use the Altera memory controller to begin with, just to save time for my client, but the DDR2 generator was unable to give me a working IP with the (wrong) pinout that I was given17:27
olofkSo out of desperation I started implementing my own controller17:27
ZipCPUSo you eventually got a correct pinout?17:27
ZipCPUI'm still leaning towards a conspiracy ... ;)17:27
olofkAnd at that point there was no time to keep fiddling with my own controller as the one from Altera "worked"17:28
olofkWe should never rule out a good conspiracy :)17:29
olofkI released the first batch of speakers at by the way. Please let me know if I made any mistakes in the descriptions17:32
kc5tjaolofk: Does Orconf move from country to country, or does it stay in the same country year to year?17:42
olofkkc5tja: The thing is that the conference is usually so wild that we are banned from ever entering the country again. That's why we move around17:44
olofkWe've been to Sweden, UK, Germany, Switzerland and now Italy17:44
ZipCPUI KNEW there was a conspiracy involved ..17:45
olofkYep. If you draw lines between the cities where we have been, you will notice a certain pattern17:46
ZipCPUI notice you only have six presentations listed.  Have others just not signed up yet?17:47
olofkZipCPU: Yep. We tend to get a sharp hockey stick though, once we release the first batch17:49
olofkLast year was crazy. Two weeks before the conference we were afraid we wouldn't fill the room, and the we suddenly had to move it to a much larger venue :)17:50
olofkThere are also several talks that we know will come, but they haven't sent in a proper submission yet17:50
ZipCPUThen I'm glad I'm coming from a foreign land--so I don't get stuck with any of that last minute busy work. :)17:52
olofkYeah, same thing when I was at the risc-v workshop. I registrered months in advance17:52
olofkI still finished the poster two days before I left though :)17:52
ZipCPUNot me, I've got my slides done.  I'll probably revise them once or twice, but I've got the basics done already.17:54
olofkI always wanted that kind of self-discipline :)18:04
kc5tjaI wish I could bring myself to finish the CPU design in a reasonable time, much less posters.18:05
mafmolofk: interesting this OpenPiton, I had no idea that opensparc was still a thing after Oracle's acquisition19:25
--- Log closed Wed Aug 03 00:00:08 2016

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