IRC logs for #openrisc Monday, 2016-08-01

--- Log opened Mon Aug 01 00:00:05 2016
stekernSMDhome1: it's an or1200 not mor1kx in the allwinner chips01:44
SMDhome1stekern: yep, but does or1200 differ from mor1kx too much that it could clock max to 400-600 mhz?02:08
stekernwell, mor1kx *do* have a longer pipeline, so a slightly higher fmax could probably be expected02:09
stekernbut all your other points are valid02:10
SMDhome1ok, but I had a feeling that nowadays it's possible to make openrisc or other not-so-complicated project to reach 1ghz freq even on 130nm process02:11
SMDhome1 but they've managed to get only ~500 mhz with 28nm though02:12
SMDhome1or 40nm02:14
stekerncritical paths is probably more related to the fmax than the complexity02:26
stekernalthough a less complex core might have less critical paths02:26
stefanctwhat's the approximate deadline for submissions to orconf2016?04:27
olofkstefanct: No deadline set up yet. We've been lucky enough the previous years to be able to fit all proper submissions that we have received07:02
olofkThough we did have to extend the conference to an extra day last year to manage that :)07:03
stefanctolofk, ok... ill try to get my boss approve the traveling then i could present our (yet unreleased) tool for automatic fault injection instrumentation into existing netlists based on verilog-perl15:20
stefanctor alternatively something coreboot-related15:21
olofkstefanct: Both sound very interesting. Hope to see a submission soon :)16:54
olofkHmm... that looked like a sarcastic smiley. It wasn't meant like that. Just that I hope you manage to convince your boss soon17:27
olofkSmileys are hard17:27
ZipCPUWoohoo!!!  After a week of hard work, my Wishbone-DDR3 controller passes its test bench, *and* builds within Vivado, *and* doesn't break my 200MHz clock/timing requirement!17:46
ZipCPU(I haven't had the guts to actually try it on my hardware yet ...)17:46
olofkZipCPU: Congratulations! Is it written completely from scratch or based on Xilinx MIG controller?18:03
ZipCPUolofk: Written completely from scratch.  No dependencies on the MIG at all.18:10
olofkZipCPU: Great! What kind of primitives are you using for the I/O?18:16
ZipCPUolofk: The controller itself doesn't include the I/O primitives (yet).  I've thought of including them, since I do have them, they're just ... not yet part of the project.18:25
ZipCPUThe Xilinx primitives I'm using include: IDDR, ODDR, OBUFDS and IBUFDS.  Everything else is (currently) inferred.18:27
ZipCPUThese are part of the connection(s) between the FPGA vendor-agnostic code and the vendor-specific code.18:28
kc5tjaZipCPU: Can your core be used for DDR and DDR2 memories as well?19:15
ZipCPUkc5tja: Good question.  I'm not doing anything with those memories right now, so it's hard to say.19:53
ZipCPUI guess my best answer would be simply this: it is open source.  All of the timing parameters are buried within it, and you are welcome to modify any other timing parameters as you see fit.19:53
ZipCPUOther than the timing parameters, there are only a couple of commands being used:19:53
ZipCPUREAD, WRITE, PRECHARGE, ACTIVATE, NOOP, PRECHARGE-ALL, and ... let's see, there's a calibration command as well.19:54
ZipCPUOne of the things I like about the implementation is that the RESET sequence and the refresh sequence are both easily adjustable.19:55
ZipCPUThey consist of simply a list of instructions, sort of like a ROM memory, where one bit in the instruction specifies whether or not a timer is to be run during the instruction.19:55
ZipCPUHence, when you start the memory, you are supposed to hold the reset_n line low (active) for 40us.19:55
ZipCPUOne line in that table specifies a NOOP for 40us.  One bit in every table entry specifies whether or not the reset_n line is to be high or low.19:56
ZipCPUThat makes reset logic simple.19:56
ZipCPUThe refresh logic is done in a very similar fashion.  Sadly, as a result, the refresh logic isn't "optimal".  I mean, it always waits for the last write operation to complete (regardless of whether one was in progress), then issues a PRECHARGE-ALL command (regardless of whether or not any banks are open, and so forth.19:57
ZipCPUI already have another controller for an SDRAM memory, I've just never done DDR or DDR2 memories.19:58
ZipCPUI just looked up the other commands: MRSET (set mode register) and REFRESH.20:05
kc5tjaI was just wondering, because at some point, I would like the Kestrel to have more than 16MB of memory.  ;)20:45
ZipCPUGlad to help!20:47
-!- sandeep is now known as Guest9096422:24
--- Log closed Tue Aug 02 00:00:06 2016

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