IRC logs for #openrisc Friday, 2016-06-17

--- Log opened Fri Jun 17 00:00:57 2016
wallentoGeneralStupid: Computer Engineering ;)02:29
wallentoSMDhome: of course it would be awesome to have an asic-proven core ready, and better testing and verification would be the key to this (beside actually taping it out)02:35
wallentobut I slightly disagree with your colleagues. ARM cores are actually not that expensive and they actively promote it for small production volumes with good pricing, I think. There are hundreds of Chinese ARM SoCs with relatively small volumes in the market..02:36
SMDhomewallento: so are there any steps taken towards verification?02:39
wallentoI think we discussed it at least ;)02:54
SMDhomeI have a short memory, sorry)02:58
wallentoSMDhome: That was meant a bit sarcastical ;)06:03
SMDwrkwallento: someone has to write a detailed testing plan and then we can make tests based on it, right?07:08
wallentoI think the first step is to have someone that really understands testing well07:09
wallentoI only know some terms, but have no real idea to be honest07:09
olofAny DPI users?08:59
-!- goyeld is now known as soiled09:19
ZipCPUDoes anyone have clock rate numbers for OpenRISC running on any Xilinx platforms?  Both in terms of fundamental clock rate, and fewest clocks per instruction?09:22
ZipCPUI think I read 50 MHz at one time somewhere google'd and online ...09:27
olofI managed to synthesize a minimal mor1kx to ~200MHz on a Virtex-6, but I think 50MHz is pretty standard for our SoCs09:39
olofAnd I know that we have some CPI measurements from dhrystone other tools somewhere. stekern or bandvig might know more09:39
ZipCPUolof: I wasn't going to go as far as dhrystone for a benchmark.  I was specifically looking for the fastest instruction clock cycle.  Dhrystone gets ... confusing.09:42
ZipCPUDhrystone depends upon cache's, branch execution delay, pipeline delays, compiler success ... it's a decent overall measure,09:43
ZipCPUbut I was looking for something a touch more ... raw.09:43
olofMost instructions are single-cycle, if that's raw enough :)09:44
ZipCPUThat's the raw I was looking for.09:44
olofI find DPI extremely confusing09:44
olofOr perhaps it's just how it's used in Pulpino09:45
ZipCPU"DPI"?  Did you mean "CPI", or "Clocks per Instruction"?09:45
olofZipCPU: Sorry. I'm talking about the method in SystemVerilog to call out to C code. (like VPI for verilog)09:45
olofor pli before that09:45
olofAll these TLAs :)09:46
ZipCPUAh ... topic change.  ;)  No problem.09:46
ZipCPUolof: Thanks for the quick answer, though: 50 MHz, most instructions take one clock, mor1kx.09:46
olofSo, the DPI c file include as dpiheader.h, which is generated when the C file is compiled09:47
olofIt seems like this is the way Modelsim wants to have it09:48
olofXilinx xsim otoh creates the DPI lib first in the xsc stage, and later on, in the xelab stage we can generate the .h file. So including it from the C file makes no sense at all09:49
ZipCPUNot a Verilator day for you?09:50
olofZipCPU: No, I've wanted to update the Pulpino cores for FuseSoC, but they started using DPI, and there isn't any DPI support in FuseSoC yet09:54
olofSo I need to figure out how to do this in a nice way that works for all DPI-enabled simulators09:54
olofRight now it looks like the API will be pretty similar to VPI09:54
ZipCPUAh!   That makes more sense.09:54
wallentoI did10:09
wallentoah, there is some more text :)10:10
wallentoI haven't looked at it in detail, but we use DPI with ISIM and verilator in parallel in lowrisc10:11
shorneHi all, I havent been talking much because of a few things, but still working on newlib and gdb patches for upstream...20:49
shorneThis is a summary of gdb/newlib issues pointed out by the gdb testsuite20:50
shorne (I have been updating it)20:50
shorneI think for GDB the failures are not big, so we dont need more fixes (unless someone else wants to :))20:50
shorneFor newlib I want to fix the compiler issues, then we should be good to go (listed at the bottom of the gist)20:51
shornein summary (newlib missing sys/mman.h, environ multiple defines, wait, rename. gettimeofday)20:52
shorneChime in if you think we dont need to touch any of them20:52
--- Log closed Sat Jun 18 00:00:58 2016

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