IRC logs for #openrisc Thursday, 2016-06-16

--- Log opened Thu Jun 16 00:00:55 2016
SMDwrkIs there any stated project goals for openrisc?10:34
wallentopromote open source ISAs is probably the most generic11:37
wallentobut I think as a community its building an open source processor with the ecosystem, to help learning how stuff works and building systems around it11:38
wallentothat would be my pitch..11:39
GeneralStupidwallento: what is your opinion about asip, especially "closed source" stuff like tensilica?12:08
wallentoasip makes a lot of sense if you really know your application/domain well12:08
wallentotensilica is probably the choice if you just want to buy something and bring it to a chip in a short time12:09
GeneralStupidwallento: what i dislike about tensilica is, you send them your "TIEs" and your whole extensions and they generate the bitstream.12:10
wallentoyeah, but if getting it to a chip is all that counts thats probably what you want to pay for12:10
GeneralStupidwallento: yes -.- but i dislike that idea.12:11
wallentotaking an openrisc or even a risc-v core, its not that you just download it, "add an instruction" and generate the bitstream12:11
GeneralStupidwallento: i dont like it to give my (probably great) idea to a company...12:11
wallentoyeah, agree12:11
wallentoprobably you have an NDA with them12:12
wallentoI just worked with Tensilica once and there with the simulators and the compiler interface12:12
GeneralStupidwallento: i know. But think about open source software, GNU Linux for example.12:12
GeneralStupidwallento: i "worked" a bit with it. The tools are great (IMHO)12:12
GeneralStupidwrite your C code, press simulate then you see, for example, there is a lot of float. click "add float" and start simulation again.12:13
GeneralStupid(that would be easy with openrisc too, but the tools make it really easy)12:13
GeneralStupidwhat i wanted to say. Look at early linux, i remember if i released a disc to eary that i got a kernel oops message and had to reboot.12:14
GeneralStupidnowadays i would say its a pretty mature operating system. Look at android or Ubuntu12:15
wallentoyes, thats right12:15
GeneralStupidi think that open hardware movement just needs time and it will be that easy with openrisc12:15
GeneralStupidtake the right (open source) tools and click on "add an instruction"12:15
wallentobut IBM didn't use Linux at that time right, so everything takes its time12:16
wallentoI think it won't even be too hard12:16
GeneralStupidi would love to develop something like this in my master thesis -.-12:16
wallentoto build such a tool12:16
wallentoit will help people a lot12:16
wallentowhen will it start?12:16
GeneralStupidwallento: i think your right but i think there are a lot of little things which i miss right now.12:17
GeneralStupidwallento: i hope september / october12:17
wallentooh, yeah, but tensilica did also not build their tools with one person in six months..12:18
GeneralStupiddepends on how good the exams work :D12:18
wallentoI can help with reviewing an expose or so12:18
GeneralStupidno, i want to do it a bit scientific... the main part should be to evaluate the results. like "is it possible to take an openrisc as tensilica replacement"12:19
GeneralStupidso i would develop software, of course but i dont think that it ends in an eclipse based tool, like tensilica :D12:20
GeneralStupidwould be great :D12:20
GeneralStupidwallento: thanks :D are you still at tu munich?12:21
wallentono, I left last year12:21
wallentobut still in munich12:22
GeneralStupidwallento: what happend? -.- bad question?12:23
wallentoGeneralStupid: didn't you get the answer?12:35
wallentoNo, I left last year12:35
wallentobut I am still in Munich12:35
wallentoyeah, and still writing up my phd thesis, so questions regarding this are bad questions ;)12:36
GeneralStupidwallento: i know this didnt help you, but i wish i would be at that point...12:37
GeneralStupidwallento: did you study computer science or eletrical engineering?12:50
SMDhomewallento: Do you agree that promoting OpenRisc ISA would be much easier if there is available core ready to be baked to asic? Collegues say it may also drop prices for arm/mips cores a little13:48
-!- soiled is now known as dickbutt17:17
-!- GOYELD is now known as goyeld17:26
--- Log closed Fri Jun 17 00:00:57 2016

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