IRC logs for #openrisc Tuesday, 2016-04-26

--- Log opened Tue Apr 26 00:00:38 2016
_franck_mithro: the purpose of jtag verilator is to debug the debug ecosystem so it doesn't matter if it is not fast01:21
mithro_franck_: I want to use it so I can connect gdb to the simulator in the same way I can the real hardware and then debug firmware running on the softcpu, hence the simulator performance is quite important.01:26
olofkmithro, _franck_ : I agree. It's a great feature to run debug in realtime on a sim target. If it's the verilator sim that is slow, I think it's just a matter of doing the serialization in verilog, so we don't have to call do_jtag every cycle01:59
mithroI think it's the cost of doing the syscall to check if there is any data on the socket but haven't looked at it closely.02:09
mithroOur target runs the mor1k at about 1MHz on a modern CPU but with the JTAG is seems closer to 1kHz or slower.02:12
olofkmithro: Ah yes. that might be the biggest cycle stealer02:13
mithroMy next test will be to only call it every X cycles02:14
olofkThat could be a good solution. We don't need to have the data available the exact same cycle that it appears on the socket02:16
olofkI think the verilog/VPI version only calls it every 1000 cycles or so02:17
olofkAnyone good with DDR3 memories? Is there any command to set them in some kind of sleep mod?04:02
LoneTech_I'd expect them to have a self refresh mode, but do you mean intentional decay?04:10
-!- LoneTech_ is now known as LoneTech04:10
olofkLoneTech: I'm thinking of some kind of power-saving mode04:11
olofkIt doesn't have to retain data04:12
LoneTechyou can find quite a bit of information in Micron's datasheet 09005aef83021ee3 (
LoneTechnot sure if that in particular is in there, been some time since I looked at it04:14
LoneTechthere's a shutdown mode in the config register04:14
LoneTechoops, that was for the temp sensor. that's what I get for looking at a DIMM rather than a memory chip04:14
mithroolofk: I know there area bunch of low power modes on Laptop DDR3 - dunno how that compares to DDR generally04:17
SMDwrkWhat type of ram controller is used in openrisc: a custom one or sort of vendor(xilinx/altera)?04:20
LoneTecheither can be used. I think the orpsoc design used one of the opencores controllers04:21
olofkI think lpddr has sleep modes, but I'm not sure about regular ddr.04:36
olofkSMDwrk: For SDRAM we generally use an open source verilog controller. For DDR memories, we generally use the one the the FPGA vendor supplies, but there has been some work on open source ddr controllers too04:38
olofkIt would be great if the FPGA vendors would support DFI properly04:39
wallentoshorne: no, or1k-src is not needed anymore, except for sim, which I will hopefully do soon05:31
shornei see thanks. I dont know much about it, but how much can the verilator simulator do that the or1ksim can?06:15
shorneor is the gap too big?06:15
shornei.e. or1ksim has gdb server06:15
olofkshorne: You can run gdb on a verilated model as well06:19
olofk_franck__ did some experiments where he used or1ksim to model the CPU and verilated RTL code for the peripherals06:19
olofkor1ksim is most likely faster than verilator, but if you need some custom RTL code, you can't use it06:20
shorneolofk: I am running gdb tests on or1ksim09:12
SMDwrkDoes anyone need some computation resourses i.e. for running tests on regular basis? I think I can share a rig w/ 16 amd cores and 32gb ram09:27
olofkSMDwrk: That could be useful. I think I need to test the bitcoin-mining abilities of my latest CPU :)09:53
olofkshorne: Ah. Cool. Is it working? Many failed tests?09:53
olofkSMDwrk: It would be great to have the ability to run more regression-tests on both the toolchain and the RTL code, but I don't think we have any easy way to set up the infrastructure yet09:56
SMDwrkolofk: I see, and is there any testing anything for orisk toolchain/cpu/soc?09:59
olofkSMDwrk: wallento has been running a jenkins instance for the toolchain.10:00
olofkWe have been trying to consolidate all OpenRISC tests from or1ksim, mor1kx development and so on in an or1k-tests repository, but we still haven't done anything with it yet10:01
mafmolofk: if it helps, you can get some inspiration from:
shorneolofk: hmm, I am trying to run the tests on the remote simulator using remote debug, but I am not sure if it works.10:27
shorneI need to setup gdb 'boards' explaining how to connect and load gdbserver on the target, but the simulator is already running gdbserver10:27
shorneI am doing something completely wrong, but a lot of tests that dont load run code are passing10:29
SMDwrkolofk: Ok, I think some sort of testing infra is a must have. I.e. at work we do have common infra in which everything is built and run10:39
shornefyi, in case anyone knows anything about gdb testsuite, this is what I am running
_franck__shorne: I think what I did was not to connect to gdbserver on the target. I think I added or1ksim as an internal gdb sim and then run tests without any connection to the remote.11:01
_franck__well, you can also find this commits in the main repo11:03
_franck__shorne and others, this the slides of the presentation I did about gdb status at orconf 2013:
olofkmafm: We have a similar repo to riscv-tests. Just that we don't anything with it :(16:15
olofkshorne: I see you got help from _franck__. The other person to talk to would be jeremybennett.16:17
mafmolofk: ah ok, I thought that you didn't have the tests themselves16:51
shorne_franck__: thanks, excellent, I knew something was wrong with my approach17:30
mafmolofk: ah, nice17:37
shorne_franck__: I guess the reason I was having problems is binutils-gdb doesnt have sim support merged from or1k-src as wallento explained earlier. Trying to work on that now18:07
mithroIs there an IRC channel which is good for discussing things like "How to efficiently implement XYZ on a Xilinx FPGA?" etc?21:14
--- Log closed Wed Apr 27 00:00:40 2016

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