IRC logs for #openrisc Sunday, 2016-04-17

--- Log opened Sun Apr 17 00:00:25 2016
olofkmithro: Did you have to override the FPGA tap ID?02:44
mithroolofk: yes03:40
-!- Netsplit *.net <-> *.split quits: trem, sandeepkr__03:56
-!- Netsplit *.net <-> *.split quits: wallento, robtaylor, simoncook03:57
-!- wallento_ is now known as wallento03:57
-!- Netsplit *.net <-> *.split quits: trem_04:12
-!- Netsplit *.net <-> *.split quits: julzmb, Amadiro_04:12
-!- Netsplit *.net <-> *.split quits: Empyrium, rokka, jeremybennett, olofk04:12
-!- Netsplit over, joins: trem_04:27
-!- Empyrium_ is now known as Empyrium04:28
olofk_mithro: Would be good to write down how to do that in the tutorial04:51
olofk_andrzejr: nexys4ddr_top seems to build now with some fixes to FuseSoC and the rmii_to_mii core06:44
andrzejrolofk_, cool. Did you check out a fresh nexys4ddr branch or switched to it from master?06:49
andrzejrboth repos have diverged quite a bit recently.06:49
olofk_Hmm... why would that be different? I cloned your repo and checked out the nexys4ddr branch06:54
-!- olofk_ is now known as olofk06:54
olofkAlright! Build is complete. Don't have any board to test it with though :)06:56
olofkOne tiny thing left to do. Unfortunately this one seems to require some major rework in FuseSoC :/07:07
olofkFuseSoC currently parses the IP-XACT file when it loads the .core file, but the file isn't there until we have fetched it07:09
olofkAnd I would like to only run fetch on demand07:11
olofkThis could be solved by having a special case where we fetch the core if the .core file contains a IP-XACT file, but it couldn't be found in the core root07:13
olofkI'm just a bit worried that this might open up other problems. Don't know what though07:14
olofkah fuck it. I'll try and see if that works07:14
olofkHa! It works. That will be good enough for now07:22
olofkandrzejr: With the latest fixes to FuseSoC, it should work now with some minor changes to your .core files07:27
olofkRemove the patches dir from xilinx_mii_to_rmii and apply this patch
olofkThe resulting bit file of course untested07:28
olofkwallento: I reviewed your vivado backend07:47
olofkHaven't tested it yet though. Got a good example project that I can use without your naming stuff?07:48
-!- Netsplit *.net <-> *.split quits: feddischson, simoncook, Amadiro11:30
wallentoolofk: unfortunately not11:33
-!- Netsplit over, joins: Amadiro11:36
-!- Netsplit *.net <-> *.split quits: aburgess12:32
bandvigandrzejr: mithro: which kind of JTAG cable do you use?12:53
andrzejrbandvig, I'm using an on-board (Nexys4) USB<->JTAG cable.12:57
-!- Netsplit *.net <-> *.split quits: aburgess_13:00
bandvigandrzejr: Nexys4 is Digilent's product. A have another Digilent's board - Atlys. Atlys also has got on-board USB-JTAG. Do you think I could use it in the same way as on Nexys4?13:03
-!- Netsplit over, joins: aburgess_13:11
olofkbandvig: Well, you're in luck. mithro just got that working yesterday :)13:30
olofkIt works by flashing the USB-JTAG converter with a custom firmware that makes it imitate the Altera USB Blaster protocol towards the USB side. Then you need to instantiate a Xilinx BSCAN JTAG Tap in the FPGA13:31
bandvigolofk: I saw yesterday discussion, but I didn't recognize that I need to re-program on-board USB-JTAG converter.13:37
bandvigolofk: perhaps, I would prefer to by Xilinx's "Platform Cable USB" and connect directly to FPGA (by instance of appropriate BSCAN). The only thing I worry if "Platform Cable USB" could be accessible from CygWin.13:43
andrzejrbandvig, olofk, I didn't have to flash anything, just set some driver options in the openocd script. But I'm not sure if nexys4 and atlys use the same cable.13:46
andrzejrWorth trying:13:46
andrzejrIt's all about the 5 ftdi_layout* calls at the top of the script.13:48
bandvigandrzejr: did you perform some reverse engeneering of Nexys4 to uderstand which kind of modification you needed?13:57
andrzejrbandvig, nope, just checked some of the existing configs. AFAIR this one:
andrzejrthe only difference is vid/pid14:02
olofkProblem is that it looks like they (Digilent) use different chips on all boards14:15
olofkOn Atlys it's apparently a Cypress FX2. On my lx9 microboard it's some Atmel MCU14:16
olofkIf it's just an ordinary FTDI chip, andrzejr's method would most likely work fine14:16
olofkbandvig: And I'm not sure it matter if you get a Platform cable. You would still need OpenOCD to understand the protocol. Not sure it does that14:17
olofkok, this is scary. The moment I started writing Cypress here, an ad for Cypress PSoC4 turned up in my browser :)14:18
bandvigolofk: I'm not sure about OpenOCD, but "Advanced JTAG Bridge" (from Advance Debug System package) should support "Xilinx Platform Cable USB"14:32
bandvigolofk: so I think the OpenOCD also should support it or it could be appropriatelly putched14:34
bandvig "patched"14:34
olofkbandvig: Oh, I didn't know that. In that case OpenOCD might support it already too14:42
wallentoI think all digilent board use the same FTDI chip and firmware14:43
wallentooh, if any of you needs a jtag<->pmod adapter, I can provide some14:44
wallentovery simple breakout board14:45
wallentoI designed it for the ARM compatible JTAG adapters, such as the Olimex one14:45
olofkOnly JTAG adapter I got is an old Actel FlashPro, and there aren't any drivers for that14:46
olofkI really should get one14:46
olofkLike the Olimex for example14:47
olofkwallento: I had to check the schematics for myself to be sure, but just as mithro says, it's not an FTDI chip on the Atlys, but a Cypress chip14:51
olofkSo Digilent uses different USB-JTAG solutions for different boards14:51
wallentooh, crazy14:52
wallentoI think they stopped this14:52
wallentoand use their board module14:52
wallentothat xilinx also uses14:53
wallentoon large boards14:53
wallentoon the most recent ones they only use their stuff14:53
wallentoas they are somehow with fossi we may bring this topic up now :)14:53
wallentobut the cypress is a nice chip14:53
olofkboard module?14:53
wallentothose SMT modules14:54
olofkYes, I guess it's time for my yearly angry tweet to Digilent about their proprietary JTAG protocol :)14:54
wallentoyou can find them on xilinx boards, such as the kc70514:54
olofkah ok14:54
wallentothey are identical to the subsystem on nexys and arty14:55
olofkThe other option is to get a HS3 (or a platform cable, but they're much more expensive) and hook up to the 2x7 connector. That one has been pretty standard for many years now on Xilinx boards14:55
wallentoby the way: I have also spoken to Trenz Electronics (
wallentothey have really nice boards14:56
olofkah. Nice. I've looked at their stuff many times before14:56
olofkYes, indeed14:56
wallentothey are part of the Librecores jury14:56
wallentonice folks to talk to14:56
wallentoThey will also be in Bologna and bring boards with them :)14:57
-!- Netsplit *.net <-> *.split quits: fotis215:33
olofkFuseSoC icestorm backend is more or less done now. Hope to push it soon17:40
-!- Netsplit *.net <-> *.split quits: sandeepkr_17:41
-!- Netsplit *.net <-> *.split quits: aburgess_17:41
-!- Netsplit *.net <-> *.split quits: andrzejr17:41
-!- andrzejr_ is now known as andrzejr17:41
--- Log closed Mon Apr 18 00:00:26 2016

Generated by 2.15.2 by Marius Gedminas - find it at!