IRC logs for #openrisc Saturday, 2016-04-16

--- Log opened Sat Apr 16 00:00:23 2016
wallentojumbo, I would suggest the Nexys4 DDR board:
wallentothere is academic pricing if you are or know a student03:26
shorneolofk: stekern: Before when we were talking dma controllers we mentioned wb_streamer, and another prehistoric dma controller05:11
shorneis that wb_dma?05:11
mithroSo, does the mor1k have JTAG debugging using openocd on the Spartan 6?05:17
shornemithro: I have been able to single step in gdb if that is what you mean05:22
shornebut on a xilinx board05:22
shorneover openocd05:23
olofkshorne: I think what stekern meant was that there are built-in DMA controllers in both the standard ethernet and VGA controller we usually use05:24
olofkwb_streamer is a standalone component05:25
olofkmithro: Yes, that should work, but you need to hook up JTAG to an external connector, not over the USB connector05:26
olofkWhich really sucks. I can't understand why Digilent can't just open up their stupid JTAG over USB protocol. The Altera equivalent is reverse engineered, so for boards like de0_nano, we can just use the regular USB connector with OpenOCD05:27
olofkIt's not very straightforward to use the Xilinx IP-XACT files in FuseSoC yet :/05:29
olofkThey define the same files in several filesets, and there isn't really a reliable way to filter that out automatically05:30
olofkBut I have actually already thought about this and the plan has been to somehow disable filesets from the .core file for cases like this05:31
mithroolofk: I have open firmware for the Atlys board05:46
mithrosorry, I'm back now - My dinner turned up06:19
mithroshorne: How did you do that?06:19
mithroolofk: Can you point me to the code around the JTAG stuff?06:20
olofkmithro: Open firmware? For the onboard MCU?06:29
mithroolofk: yes, it emulates a Altera USB Blaster device06:29
mithroolofk: works well with openocd06:29
olofkCool :)06:32
mithroolofk: I was sure I had mentioned that before?
olofkI guess the next step then would be to instantiate a Xilinx bscan device then and connect that to adv_debug_sys06:32
olofkI wasn't aware. Do you know if that works for other boards too? I have an lx9 microboard with the same issue06:33
mithroolofk: The lx9 microboard was done by the makestuff guy?06:33
mithroI even have udev rules which will make the Atlys appear in the right way on plug in06:34
mithroAnd we even have debs at :P06:34
olofkSo to sum it up. The current code for the Atlys OpenRISC SoC in FuseSoC uses PMOD->(opencores jtag tap)->adv_debug_sys06:34
olofklx9_microboard is another Digilent board06:34
olofkhaha. Nice. If I only had more time, I'd love to look that up in more detail :/06:34
mithroolofk: does it have a Cypress FX2 on it?06:35
olofkWith your firmware it would be MCU->(Xilinx BSCAN)->adv_debug_sys06:35
shorneolofk: I see, i am looking at wb_dma on opencores, I looked through wb_streamer too06:36
mithroolofk: Yeah06:36
olofkmithro: Haven't checked. Didn't know there was an FX2 on the Atlys actually. Thought it was some general ARM MCU06:36
mithroolofk: It looks like it has an Atmel06:36
shorneby half?06:36
olofkshorne: wb_dma is pretty old. I looked at it when I did wb_streamer, but I didn't think it was worth extending.06:37
shorneso.. I see wb_stream has both read and write, what do you mean by half dma/06:37
olofkshorne: wb_dma has two wb master ports, so it can read a portion of the memory space and copy to another part06:37
mithroolofk: so adv_debug_sys is the tool running on the computer or the part?06:37
shorneI see, but wb_stream just has one port06:38
olofkmithro: It's the RTL code for the debug interface that we connect to OPenRISC06:38
shorneto do dma from one wb-client to another wb-client you need two06:38
olofkshorne: Yes, exactly, one read and one write06:38
mithroolofk: does it interface to the mor1k? or only the older implementation?06:39
shorneok, that makese sense06:39
olofkshorne: So it would be memory -> wb_stream_reader -> wb_stream_writer -> memory06:39
olofkmithro: It works with or1200, mor1kx and the Pulpino guys use it for their RISC-V as well06:39
shorneolofk: and the stream protocol  would just be a small intermediary step, nothing needs to be there really06:40
olofkshorne: In theory you should just be able to connect the stream ports to each other, but I'm not sure I have actually tried it. Should do a small testbench to try that06:40
shorneyeah, Ill try to wire them up and simulate in a small test06:41
olofkThe drawback would be that you need to set up both the read and write parts to do a transfer, but I structured the RTL, so it should be possible to create a wrapper that sets up both at the same time06:41
olofkshorne: I have a simple bare-metal driver for the streamer too if you are interested06:42
olofkmithro: There is a host client part for adv_debug_sys as well, but we use OpenOCD instead06:43
mithroolofk: okay06:43
olofkThere is another cool feature in adv_debug_sys too, so that you can tunnel a UART over JTAG06:43
mithroIs the the current version at,adv_debug_sys the current?06:44
olofkIt works with OpenOCD as well, but there is some issue with the IRQ, so when Linux switches from polling to IRQ mode it stops working06:44
olofkmithro: I've done some fixes to my copy at github06:44
mithroolofk: okay, so should use that?06:44
olofkI'm hoping to get the stuff from pulpino merged in here as well in the future06:45
olofkSince OpenCores refuses to move from password protected svn repos and it's difficult to fix other people's cores I had to fork it :/06:45
olofkmithro: If you want to try it in simulation, you can use the mor1kx-generic system in FuseSoC06:46
olofkIf you run with --enable-jtag-vpi, the RTL will set up a socket connection which you can connect to from OpenOCD06:47
olofkThere's a driver in mainline OpenOCD for that06:48
mithroolofk: okay06:56
mithroIts going to take a while to figure out how I can integrate this into MiSoC06:56
mithroWhat the JSP?06:57
olofkmithro: Hmm..06:58
olofkAhh.. that could be JTAG Serial Port06:58
olofkmithro: For MiSoC you already use mor1kx as a blackbox, right? Maybe you could just add an option to also instantiate an adv_debug_sys instance together with that07:00
mithroolofk: that was my thought :)07:00
olofkThat gives you the freedom to select jtag_tap, bscan, altera_virtual_jtag or jtag_vpi as your JTAG connector07:02
olofkI guess you could even do a UART-> JTAG adapter, so you can send JTAG commands over a UART. That would be cool07:03
mithroolofk: well, the jtag connector bit should probably happen at the higher level as misoc supports a wide range of boards07:03
olofkmithro: Yes, exactly, that would be a target-specific thing07:03
shorneolofk: I might be, I was reading through the linux driver, but at first I would just git up the verilog test bench and check in vsim07:05
mithroI had our bios booting on the or1k but I've broken it somehow07:05
shornebtw, last time I tried running vsim on fedora it was not working. Does anyone know the state now?07:08
shornenot working meaning, some libs were not longer available, cant remember exacts07:08
shornefedora 2307:08
olofkshorne: You can use icarus07:08
olofkI just noticed that I haven't pushed wb_streamer to the FuseSoC core library. Weird07:09
shorneolofk: I was reading from your repo07:10
shornethat was no problem finding it07:10
shorneThanks ill try icarus, I have just been using the quartus bundled tools now, better try the free ones07:11
olofkshorne: Are you using FuseSoC?07:12
olofkThen you can just add the path to your downloaded wb_streamer repo (or add --cores-root=/path/to/wb_streamer to the command line) and run fusesoc sim wb_streamer07:15
olofkor fusesoc sim wb_streamer --vcd to get a VCD file07:15
olofkfusesoc sim wb_streamer sim --help to get all supported options07:16
olofkfusesoc sim wb_streamer --help07:16
mithroolofk: where can I find the adv_debug_sys wired to the cpu?07:26
olofkI think we have a system as well that uses JSP, but I'm not sure where that is07:28
shorneolofk: cool, I just knew fusesoc build up until now.  Is there a command to generate the wb_intercon too? or need to run the script manually?08:19
shorneI used fusesoc pgm too :)08:21
mithroolofk: do you have any examples of using the xilinx jtag adapter thingy?08:27
mithroolofk: It's kind of interesting that my code emulates an Altera USB Blaster which means it might work with the non-openocd stuff in adv_dbg_if08:29
mithrooh it looks like that doesn't support the spartan 6 anyway...08:30
olofkshorne: There is no mechanism for regenerating wb_intercon automatically yet. It's been on my todo list for a few years, but now we're getting close actually :)08:37
olofkmithro: Don't think I have any examples unfortunately08:37
olofkmithro: Ah.. you still need support for xilinx bscan in OpenOCD?08:38
mithroolofk: hrm?08:39
olofkOr did I misunderstand?08:39
mithroolofk: The code at doesn't support the Spartan 6 BSCAN module...08:58
mithroso, this seems to be kind of maybe compiling08:59
mithroolofk: once this has compiled, I should see the debug interface in a jtag scan?08:59
olofkmithro: JTAG is mostly magic to me, so I'm not sure09:18
mithrookay :)09:18
olofkBut yes, you would need to find an instance that works for Spartan6, and then hopefully you should see at least the JTAG tap09:18
mithroolofk: so, what would you "do" on the openocd side?09:19
olofkBut I'm not sure if you need separate OpenOCD drivers for the different JTAG taps, or if they are just protocl ocnverters09:19
olofkmithro: I run this for the de0_nano -> openocd -f interface/altera-usb-blaster.cfg -f board/or1k_generic.cfg09:20
mithroolofk: okay great!09:20
olofkBut maybe you need to change the JTAG id somewhere. _franck_ is your friend here :)09:20
olofkIt's really cool if this works09:21
olofkBut the best thing would of course be if Digilent just opened up their protocol so we can use the same procedure for the other Digilent boards too09:21
mithrowell, now I need to figure out wtf a FPGATAPID is :P09:23
mithroIt seems like I didn't break the core, my firmware still boots....09:32
mithroolofk: I think it kind of found the tap.....09:35
mithroLooks like someone might have added SPARTAN6 support...
mithroHeard of aura-soc at all?09:42
mithrohrm... the fact that he is driving both TMS and TDO with debug_tdo_i makes me think this might not work...09:43
mithroLets test random code on the interwebs :P10:08
mithroI'm pretty sure those comments are wrong....10:09
mithroso I think I've set the FPGATAPID correctly now10:33
mithrobut it is very unclear to me if openocd is correctly talking to the core or not10:33
mithrooh - it might be!10:35
mithroChip is or1200.cpu, Endian: big, type: or1k10:35
mithroNow to fix the reset...10:35
mithroolofk: so, once I have openocd kind of working, how do I actually connect gdb to it or something?10:36
mithroWant to inspect the registers and stuff...10:37
mithrooh, when is _franck_ generally around?10:40
mithroGetting closer I think...10:44
wallentomithro: you can have a look at the de0 nano tutorial11:27
wallentoonce you have "Chip is or1200.cpu, Endian: big, type: or1k", the rest is the same11:28
olofkmithro: This is great!11:35
mithroI broke it again....11:35
olofkBut it makes me so sad to see that you find all these random forks with one fix each on the internet. This is one of the main things I wanted to fix with FuseSoC11:35
mithroolofk: yeah, I frequently find people's patches and send them upstream for them11:37
mithroI'm not sure how to debug the burst read stuff11:38
mithroThe error sounds like it is failing to read stuff from the wishbone bus?11:42
mithroWhich I assume is when the adbg_top is acting as a master on the wishbone bus?11:43
olofkmithro: Yes, that's correct11:43
mithroWhy is it trying to read 0x400 ?11:43
olofkadv_debug_sys has several interfaces. One is used to control the CPU directly, for things like stopping and starting the CPU and read internal regs. The other is a wishbone master that you connect to you regular memory bus11:44
olofk0x400 is one of the exception vectors, right?11:44
olofkCan't remember which one11:44
olofkInstruction page fault according to the spec11:44
olofkNo matching PTE found in page tables or page11:44
olofkprotection violation for instruction fetch.11:44
olofkFuck knows what that means. Probably something with computers11:45
olofkSo are you doing anything to get this error, or does it happen when you connect?11:45
olofkAnd what SoC are you using? Is it a modified version of the FuseSoC system, or a MiSoC-based one?11:46
olofkI agree that it feels like you're close, so it would be cool to get this working11:47
mithroMiSoC based one11:47
olofkmithro: Is this the current situation in OpenOCD?
mithroolofk: no, gotten further than that11:49
mithroThat is what happens if my CPU is already halted when I call openocd11:52
mithroHowever, if I try and use openocd while the CPU is running, it fails when it tries to "save the context"11:53
olofkmithro: Could the CPU be reset? That's a classic :)11:54
olofkIIRC you need to separate the system reset and the debug reset11:54
mithroolofk: what do you mean?11:54
olofkCheck here for details
mithroYou guys do11:55
mithroassign or1k_rst = wb_rst | or1k_dbg_rst;11:55
mithroolofk: which I also do11:55
olofkWhere wb_rst is a power-on reset more or less and or1k_dbg_reset is controlled from adv_debug_sys11:55
olofkah ok11:55
olofkThen it's not that11:55
mithroolofk: we have a different RESET_PC than you?11:56
mithroso, it seems to be failing in the "int shift = find_status_bit(in_buffer, STATUS_BYTES);" when doing the read11:58
olofkJust a thought. Maybe you need to enable some options in mor1kx. stekern is the expert here11:59
mithroDoes "ocd_or1200.cpu ocd_or1200.cpu cget -endian" actually cause anything to be read out of jtag?12:00
mithroWhat is12:02
wallentomithro: richard herveille wrote the most recent adv_dbg_sys variant, he fixed it and improved the code a bit12:05
wallentoYou are right, this needs to be fixed up.12:05
wallentoI will release a preview of opensocdebug the next weeks12:06
wallentofor the arty and nexys board12:06
wallentothere the debug transport is UART, which is much faster12:06
wallentoturnaround is better12:06
mithroTODO: Real hardware tests12:06
wallentoits in silicon12:07
wallentoI think this is what this means12:07
mithrowallento: so, should I be using that code rather than the one olofk pointed me too?12:08
mithroIt might be working!~@?12:12
wallentomithro: I would give it a shot12:12
wallentobut seems you don't need to :)12:12
mithroTurns out you should enable the debug unit before trying to use it I think :P12:13
mithrowallento: ../or1k-dev.tcl doesn't appear to exist anywhere....12:14
mithroWell, I appear not to have or1k-elf-gdb12:19
wallentothis is statically linked, so it should run everywhere12:21
mithrowallento: you guys seem to have binutils and gdb in the same repository?12:25
wallentoyes, thats the same upstream12:25
wallentoits the standard binutils-gdb repo12:25
wallentoI think they are in the same because they share the bfd and opcodes stuff12:26
mithrowallento: interesting, the tarballs they produce look very different...12:27
wallentoI think its filtered then12:27
olofkmithro: This is a historical thing where they used to have everything in the same repo. They have split out gcc (I think) since then12:27
olofkAnd currently upstream binutils-gdb repo lacks gdb for OpenRISC12:27
olofkBut I don't really use that12:28
olofkYou can do most stuff directly from OpenOCD12:28
olofkLike loading programs, reading and writing memories and registers12:28
wallentoactually openocd supports more than gdb I think12:28
olofkMy daughter demands computer time now. bbl :)12:28
mithroit seems to be working...12:32
mithrohow do I step? I thought it would be stepi/nexti?12:32
wallentostepi is on assembly level12:33
wallentodid you see this:
wallentomithro: nice!13:08
olofkmithro: Great!13:09
olofkwallento: Cool!!13:09
wallentoI don't like the layout it generates, but I assume this is something the user should do with graphviz then13:09
wallentothis is just dot -Tpng <in> > <out>13:09
_franck_mithro: I guess you don't need me anymore :)15:51
_franck_FYI, I think andrzejr did use OpenOCD with a Digilent board and it's original firmware/interface15:52
andrzejr_franck_, mithro, yes, it worked just fine.15:56
andrzejrused that openocd script:
andrzejrand this top level rtl:
olofkandrzejr: What do you think, should we add an extra_files option to the logicore provider?16:16
andrzejrolofk, I guess so.16:17
andrzejrI don't mind changes, my version was just a bare minimum to get it working.16:18
olofkandrzejr: I like minimum. It means less things that can go wrong :)16:21
olofkandrzejr: logicore provider pushed. That only took about a year :)16:46
olofkandrzejr: I saw this patch also. I think you can drop it since FuseSoC supports setting library names now
olofkYou need to update the core file though16:48
andrzejrHave you got any examples?16:48
olofkIt's logical_name16:49
olofkWeird name, I know, but that's what it's called in IP-XACT16:50
andrzejrI meant examples of cores generated with logicore :-)16:52
andrzejr(but the libraries are useful too)16:53
olofkI have a few that we use at work, but nothing pushed16:53
olofkSo your mii_to_rmii core might be the first one16:53
andrzejrdoes it only need extra_files ?16:54
olofkWhich one?16:54
andrzejrmii_to_rmii. But this one doesn't need any extra files. What did you mean by "you need to update the core file"?16:57
olofkandrzejr: Oh, I mean for the logical_name stuff17:03
olofkTo drop the patch17:03
olofkandrzejr: I'll just do the same change to the coregen provider and push it now17:06
andrzejrOK, thanks. I need to go through by bit-rotted code and update it to the new version of orpsoc-cores and fusesoc.17:09
olofkThanks for the patches, and for your patience. Sorry that it's taken so long17:09
andrzejrwallento, I've seen your nexys4 repo. I see you chose to generate ddr i/f with vivado (that's is good decision, given how much headache coregen version gave me)17:12
wallentoyes, I still use yours as reference17:13
andrzejrbut how are you going to use axi4 interface17:13
wallentothere is an wb2axi I started17:13
wallentoactually I am wiring it up at this minute :)17:13
wallentoI tried to split it up17:13
andrzejroh, that's cool.17:13
wallentothere is a "board core", like nexys, arty, de0nano17:14
wallentothey encapsulate all IP17:14
wallentothen there is mor1kx_soc, my various optimsoc toplevels, pulpino, name it17:14
andrzejrmy wb2ui was another source of problems :-) I hope you managed it better.17:14
wallentoand both are then just wired by a toplevel17:14
wallentoyeah, I made the same experience17:14
wallentoI had a student that spent multiple months on wb2mig for the XUPV5 board17:15
wallentois was a pain17:15
wallentotiming was never met and we always had functional errors17:15
wallentowith the AXI itnerface I can trust to an interface I really understand :)17:15
wallentoand the wb2axi is dumb for the start17:16
wallentothe biggest issue that you cannot handle bursts properly17:16
wallentobecause linear bursts are undetermined in length17:16
andrzejryeah, I wish mor1kx supported axi natively.17:16
wallentoI started it a while ago17:17
wallentobecause I wrote an AXI interface for the Cortex-M0/M1 when I worked at ARM17:17
wallentoand I worked on the mor1kx storage path17:17
wallentobut somehow I never focused on this part17:17
andrzejrMy wb2axi almost worked, I fixed some errors that were only visible in HW (that's why diila is instantiated). But even then I was hitting some issues with bursts enabled.17:18
wallentoah, okay, where is it?17:18
andrzejrsorry, wb2ui17:18
wallentoyeah, this is painful17:19
wallentoI already spent like half an hour udnerstanding the clocking from the spec :)17:19
wallentoI currently try to simulate the whole design17:19
andrzejrwhat simulator do you use?17:20
wallentobut I am not sure if I can trigger the DDR model from tcl17:20
wallentobecause of copyright stuff17:20
wallentoxsim or isim or whatever this thing in vivado is called :)17:20
wallentoso, for the first I am just running stuff from the user interface17:20
wallentobut have no clue if I can do it as a sideproduct17:21
andrzejrtry the new logicore (vivado) provider olofk just pushed. With coregen (ise) I had to add some extra files, though.17:23
olofkThe pulp guys put AXI buses on their OpenRISC core (or10n) from the beginning17:23
wallentoI think I will do this sometime in 201617:24
olofkI really really really hate Xilinx's UI bus. It is underdocumented and contains subtle changes between the FPGA families and ISE/Vivado releases17:24
andrzejrafair lowrisc is generating ddr i/f using vivado.17:24
wallentoyes, it is adopted from there actually ;)17:25
wallentobut they use another ddr model17:25
wallentofor verilator sim17:25
wallentoI would prefer jsut to generate it17:25
wallentobut if I run synthesis it does not generate the model17:25
olofkandrzejr: I tried to regenerate your nexys4ddr_ddr2 core with the pushed coregen provider. It works even though I don't add the .prj and .cgc file. Do you know if this means that they are not needed, or if the generated core turns out bad?17:27
wallentoI think the prj is always necessary17:28
wallentoit contains the pins, right?17:28
olofkThat is what I remember too17:28
andrzejrafair there were some difference (ddr3 vs ddr2 if I remember correctly)17:29
olofkYep, I just diffed with and without the prj file. It just randomly assigns pins without it17:29
andrzejrwithout extra files some settings were lost17:29
olofkAnd gets the clock wrong17:29
olofkAlright. Then we know that extra_files work at least :)17:29
olofkandrzejr: Trying to rebuild the whole nexys4ddr_top now17:31
andrzejrnaah.. I would be surprised if that still worked.17:32
wallentoso, guys, I am off to bed now, I will commit some stuff the next week I think for the nexys board module and wb2axi17:32
andrzejrwallento, thanks. I'm eager to try your code17:33
olofkwallento: Cool17:33
olofkandrzejr: I'm having problems regenerating the mii_to_rmii core17:36
olofkahh.. I think it's because of the stupid idea of putting the Vivado version in the xci file17:37
olofkok, solved half of the problem :)17:46
olofkandrzejr: First problem can be solved by adding upgrade_ip [get_ips xilinx_mii_to_rmii]17:48
olofkafter read_ip17:48
olofkBut unfortunately this upgrades the ip from v2.0 to v2.0.8, so all paths change17:49
olofkActually... I think we can get around this by getting the files from the IP-XACT file instead17:49
olofkBut that doesn't work yet in FuseSoC. Need to patch a few things, but I got most of it working yesterday so it's not too much of an issue17:50
olofkoh... my ipxact parser doesn't fetch logicalName from the XML file18:02
olofkI give up. Close, but not there yet18:16
olofkBut I think it will be nice once it's done18:16
olofkThen we won't have to list the files as long as coregen/vivado generates an IP-XACT file that we can use to parse the file list18:17
--- Log closed Sun Apr 17 00:00:25 2016

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