IRC logs for #openrisc Saturday, 2016-03-26

--- Log opened Sat Mar 26 00:00:52 2016
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GeneralStupidhey, anyone saw that fusesoc "issue" ?12:47
GeneralStupidi wont reply for that. I needed that too and i just copied the Board directory... (yes, thats a really nice approach)12:49
wallentoyes, I wrote it13:44
wallentoI am not sure if there is a good idea for that13:45
wallentoolofk: saw your tweet regarding system verilog13:58
wallentowhich tools do you have problems with?13:58
wallentoI exchanged a few mails with Andreas from Pulpino and Wei from lowRISC to find best practices13:59
wallentowe still need to put the summary somewhere13:59
wallentothe most stupid tool is XSIM14:01
wallentothis is a blocker for all interfaces stuff14:01
wallentobecause if you connect through an interface it usually selects a random one of that type from somewhere in your system..14:01
olofkwallento: icarus didn't handle always_comb, class and several other things I can't remember now18:01
olofkxsim just gives me a cryptic error now18:03
olofkverilator might actually be quite close. Now I get some kind of width error in one place that I don't understand18:04
olofkI have hacked quite a lot in some of the files to work around some of the basic issues18:05
olofkFor example, I have removed the riscv_tracer, since none of the tools liked that one very much :)18:05
olofkAnd I removed all asserts to make verilator happy18:06
olofkAnd replaced some of the always_comb with simplified constructs to make icarus happy.. until I realized that it wouldn't parse the other code anyway18:06
olofkAnd of course I had to remove the VHDL uart18:07
olofkI give up now. No idea how many errors left to fix for verilator support18:17
olofkBut I think that pulpino would be a nice target for verilator18:17
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--- Log closed Sun Mar 27 00:00:53 2016

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