IRC logs for #openrisc Friday, 2016-03-11

--- Log opened Fri Mar 11 00:00:29 2016
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mithroSo, are there instructions somewhere on how to build a recent GCC for targeting or1k?  - I'm looking at -- Is better?01:49
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shornestekern: omg, your idea about the sdram was spot on04:28
shorneI changed 2 setting, 1 switch clk param to 50 (actual clock is 100 but to allow 32ms refresh), just put cas to 3 to be safe04:29
shorne2 set cas to 304:30
shorneit boots like a charm now04:30
stekernI was actually referring to some lower level parameters, but relaxing at that level ofc works too04:31
shorneI see, I was booting the old image which was giving serial output and it was dumping stacks, and some of the data just seemed wrong. So it was leading me more towards a memory issue04:33
shornetrying my 4.5 image now04:33
stekernyou can play with the phase settings in that04:33
stekernjust open it in the megawizard in quartus04:34
stekernI think we slightly tuned them before because someone saw some issues04:34
shorneoh, the pll settings, I think it should be ok, I wrote an sdram controller for this board a few months ago04:34
shornehad it ad same phase and 133Mhz with no issue04:34
shornebut it was running 32ms refresh04:34
shorneI noticed the wb_sdram_cntrl seems to hardcode to 64ms04:35
stekernfeel free to post a patch that makes it a parameter ;)04:35
stekernI wrote wb_sdram_ctrl against the spec for the memory on the de0_nano iirc though04:36
shorneyeah, the spec sheet has 2 grades A1 and A2, one has 64 one 3204:37
shornefor some reason I set to 32 when I wrote mine04:37
shorneI think I found it was the lower grade, not sure04:38
stekernoh... perhaps they actually changed the chips on the newer boards to lower grade then?04:38
stekernI can't remember anything about different grades back when I wrote it, but it was a "while" ago, so that doesn't really mean anything04:39
shorneIll submit a patch for the sdram controller04:47
shorneany testing you do other than the bench in the core?04:47
shorneAlso, I might as well submit a patch to bring linux up to 4.504:48
shornebut that wasn't very hard04:48
shornejust git merge04:48
shornenow time for some fun..
stekernyeah, I've been syncing the tree sporadically, usually any conflicts are very straight forward06:35
stekernI can sync it to 4.5, especially since I have a board setup to test on now06:35
stekern(and fix the bug that I noticed the other day at the same time)06:36
mithrostekern / shorne: What does "linux on OpenRISC" actually give you these days?06:39
mithroIE What type of peripherals are supported? (If anything more then a UART?)06:40
stekernspi/i2c/framebuffer/ethernet etc06:41
mithrostekern: cool, framebuffer+ethernet are supported on which devboards? The Atlys?06:44
mithroAny others? It sounded like shorne was working on a DE0 Nano?06:46
shornemithro: I am on de0 nano, it supports spi/i2c/flash07:03
shornethere are also gpios07:04
shorneI have a dac circuit hooked up to my de0 nano, I have been working on getting it up to I could write a simple sound card07:04
shorneI notice there is an ac97 core in opencores, so I might start with that07:05
shorne*I have been working on getting linux up so I can write ...*07:05
shorneI bet you could get a frame buffer on de0 nano using the gpio pins, not sure how many LEs the current SOC is using though07:08
shorneTotal logic elements : 10,789 / 22,320 ( 48 % )07:08
shorneplenty of room left07:09
mithroI have an Atlys board, so guess it easier to use that07:10
mithroAnyone have the time that if I send them a Opsis board (which is pretty similar to the Atlys board) they would get it working on FuseSoC?07:14
_franck__mithro: ethernet+frame buffer are also supported on Altera NEEK board07:25
stekernshorne: I have a lot of cruft attached to my de0_nano:
shornestekern: cool, vga, ps/2?, several serial, sdcard07:36
stekernand sound07:37
shorneI see, thats the bottom right, how are you driving it? do you have an ADC? or just doing PWM?07:38
stekernit's not serial though, it's atari joystick (aka TAC-2) interface07:38
stekernit's just a RC filter on one pin07:39
stekern"documentation" of the extensions07:39
shorneMy first project was pwm
shorneWell, one of the first07:41
shornethen I bought and ADC, basically spi interface07:41
shorneThen I wrote and sdram controller
stekernI think minimig (which I used the extensions for) is using a sigma-delta converter07:42
shorneah. I meant dac, I bought dac, the adc is on the board07:43
shorneI made a littled sound recorder, preamp -> adc -> sdram -> dac -> amp -> speaker07:43
stekernnice ;)07:44
shornetrying to just use all the parts of the board07:44
shornebut my code is all very minimal07:44
shorneA friend of mine is making a few minimigs07:48
shorneits cool what you can do with some resister ladders and rc filters07:49
shornestekern: how much more fpga space is needed for SMP?08:03
shornejust about 1 more core? or is there an apic needed as well?08:04
stekerncan't remember, but I've run a 4 core version on de0-nano at least08:04
stekernor was it only dual...08:04
stekernanyway, I've tested smp on de0_nano, so it is definitely possible08:05
shornegood to know08:05
shorneare you working on anything specifically now?08:05
stekernI haven't had much time for hobby-projects lately, unfortunately08:11
shorneme too, but just need to get my mind off work lately08:12
wallentoshorne: I think there is no apic, but all irqs connected to one core11:46
stekernwallento: all interrupts where connected to all cores12:29
stekernbut only one core has them masked12:30
stekernyou need a seperate (global) timer and a ipi core though12:31
stekernshorne: I have an (old) orpsoc-core branch with multicore support here:
wallentoah, right, thanks, stekern12:32
wallentoI also have a de0-nano finally and want to get this stuff running again12:32
wallentoand update our various tutorials..12:33
stekernone thing we need is the gdb cheat sheet with latest info12:33
stekernI found myself struggling to remember how to even connect to openocd with it12:34
shornestekern: I went through a lot of gdb commands to figure out what was going on17:03
shorneinfo reg dmmucfgr17:03
shorneinfo registers system17:03
shorneinfo reg dmmu17:04
shorne(to see the actual tlb dump)17:04
shorneI could put together a cheatsheet with example outputs17:05
shornewho approves accounts on opencores?19:06
shornemeaning the mediawiki19:07
--- Log closed Sat Mar 12 00:00:30 2016

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