IRC logs for #openrisc Saturday, 2015-12-19

--- Log opened Sat Dec 19 00:00:08 2015
olofk_franck_: I'm updating the pull request now. This time it's really good :)14:13
olofkhmm.. Maybe I should have used if(listenfd) in the last commit14:24
bandvigstekern: I've got a question related to ICACHE/DCACHE refill and DCACHE write operations.16:01
bandvigstekern: In mor1kx caches are virtually indexed and physically tagged. However, it looks like for refill & DCACHE write the physical addresses are used for indexing way/tag RAM.16:01
bandvigstekern: Is this a bug or I'm wrong?16:02
stekernI would hope you're wrong, but could you point me too where you are seeing that?16:03
stekernbandvig: ^16:03
bandvigstekern: For example, in ICACHE way_waddr[i] = wradr_i[WAY_WIDTH-1:2] (line 199) and  wradr_i is physical address (= ibus_adr in FETCH).16:07
bandvigstekern: And tag_windex = wradr_i for refill. For read tag_windex = cpu_adr_match_i, but cpu_adr_match_i is physical if IMMU is on.16:11
stekernah, yeah, but paddr == vaddr for the bits that are used16:14
stekernyou can't create a way that is larger than the page size if you want to use mmu16:15
bandvigOk, understood.16:18
bandvigOne more question. Why defauil assignement in DMMU/IMMU looks like phys_addr_o = virt_addr_match_i[23:0]; i.e. only 24 MSB are used?16:20
bandvigMSB -> LBS16:20
olofkNew blog post
olofkThe world's least popular blog. After two and a half years, I haven't even got a spam comment22:46
olofkI'm starting to suspect that people are doing other things than reading my blog23:02
olofk...on a saturday night23:03
olofkLooking at adding FuseSoC support for rocket, but it looks a bit messy23:33
olofkBut this looks interesting
olofkMaybe something that can be used with verilator23:36
--- Log closed Sun Dec 20 00:00:10 2015

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