IRC logs for #openrisc Friday, 2015-11-13

--- Log opened Fri Nov 13 00:00:07 2015
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heshamolofk: Except for uart datawidth=8, everything is modified according to your comments. Please have a look.09:03
olofkhesham: Thanks. I'll pull the patch09:25
olofkBut wb_data_resize_must be fixed, because I think this won't work when we try to access registers with lsb != 0009:26
heshamolofk: Indeed. I had problems with GPIO also due to endianness09:27
heshamAnd SPI...09:27
heshamBut that's for Atlys board not the Icarus one.09:27
olofkHmm.. so how to fix this? Should I swap sel, data or both?09:31
olofkhesham: Just to be sure, you're using a little-endian wishbone bus?09:32
heshamolofk: I am managing endianness by setting up the appropriate sel bits from vscale09:33
heshamSo yes, endianness is handled correctly from vscale side if that's what you mean.09:34
olofkI'm getting headaches evertyime I think about endianness :)09:34
heshamSame here09:34
heshamI had to debug both SPI, UART, and sb/lb instructions due to this issue09:35
olofkSo... maybe it's enough to reverse sel in wb_data_resize to fix this09:35
heshamAnd it's because of endianness09:35
olofkI'm going to do a middle-endian CPU some day09:36
olofkThat will really mess things up09:36
heshamMaybe a it's better to add an ENDIANNESS parameter or something09:36
olofkDon't have time to look at this now, but I'll try to fix this asap. Help is appreciated from anyone who feels comfortable with endianness09:37
olofkYes, that's what I'm thinking. And a field in wb_intercon.conf to set this09:37
heshamyes that would be better.09:38
heshamDid you make other comments on the recent changes?09:38
olofkNot yet. I'll take a quick look before I pull the patch09:39
heshamOK, thanks for the comments.09:40
olofkLooks good. Thanks for the patches. I'll pull it now09:41
heshamI had a look at picorv32 core you added to see if it can work like vscale, but the core contains its own AXI-memory.09:43
heshamThe next steps maybe getting the SREC loader working.09:44
heshamI am also thinking of adding the hello world assembly/C program to vscale-generic/sw like with the bootloader.09:44
olofkhesham: Yeah, it would be nice to try the SREC loader in a testbench09:58
heshamolofk: Would it work within a simulator? If so, I am not sure how it will get its input. I only tried it with minicom/FPGA.09:59
heshamThe Icarus UART core model doesn't support reading data I guess.10:00
olofkhesham: There are probably a few options. I've been considering adding a VPI module that connects to a socket, so that you can send stuff over telnet to the simulator10:01
olofkThat's more or less how jtag_vpi works already10:02
olofkAnother option is to just read stimuli from a file10:02
olofkBut sockets are cooler :)10:02
heshamI think that's similar to how or1ksim loads linux10:02
olofk...but more complicated10:02
heshamAnother option is to just get it running on FPGA :)10:03
olofkhaha. I've never been good at simple solutions :)10:03
olofkBut for debugging, it would be nice to simulate it10:04
heshamWell, it works on Atlys, if you wanna give it a try let me know.10:04
heshamYeah sure, I've been debugging it using Atlys Leds only :/10:05
olofkSure. I don't have an atlys board, but I definitely want to try it whenever we get a port to de0_nano or something like that10:05
olofkThe ordb2a board didn't even have LEDs. That was really annoying when nothing works at all10:05
heshamAnd I thought debugging using LEDS was terrible...10:06
heshamI think if we got an Atlys port running, it would just work on de0_nano.10:07
olofkYes. More or less10:07
heshamIt's a matter of rx, rd constraints only I guess10:07
heshamAnd those have nothing to do with the core itself.10:07
olofkhesham: An endianness question... when you use a byte-read instruction, do you expect the data to be in bits [7:0] or [31:24]?10:08
heshamThat's why I set sel to 0x1 instead of 0x810:08
olofkhmm... always [7:0], even if you read from address 0x1, 0x2 or 0x3?10:09
heshamIt's shifted this time10:09
olofkSo address 0 => 7:0, 1 => 15:8, 2 => 23:16, 3 => 31:24 ?10:10
olofkJust want to be really really sure :)10:10
heshamYes if you're loading/storing a byte10:11
heshamSREC writes a big endian address too, so I had to handle this.10:12
olofkhmm.. that link you sent me, it looks like sel can only be 1, 3 or f. Is that correct?10:12
heshamFor a read operation yes.10:14
wallentoolofk: are you ready for the next level of markdown?10:14
heshamolofk: 1 -> lb, 2 -> lh/lhu and F -> lw10:14
olofkWishbone doesn't work like that. For a byte-read operation of an address, you need to set the two lower bits of the address to 00 and instead set the correct bit in the sel field10:15
olofkwallento: That sounds really scary10:15
wallento ->
olofkhesham: , so for example, to read byte address 0x5e, you set address to 0x5c and sel to b001010:16
heshamolofk: Yes, but since vscale core is doing the same operation, I had to keep wishbone work this way.10:16
heshamvscale is loading the entire word and shifts it according to the load size10:17
heshamI can disable this from vscale and make wishbone work as you say10:18
olofklunch now. bbl10:18
olofkI think you need to change this, because it will not be compatible with wishbone slaves otherwise10:18
heshamIt's only done for memory read operation10:19
heshamFor UART, it's behaving like what you said, I had to disable it from vscale also.10:19
heshamI'll see if that can be changed without breaking other operations.10:20
juliusb_stekern: ah, they're the pretty slides the hardcaml guy was using?!10:25
juliusb_Andy Ray10:25
juliusb_nice stuff10:26
stekernjuliusb_: ???10:35
olofkhesham: Hmm... there might actually be a bug in the memory controller then. It shouldn't allow byte accesses like that11:00
olofkNeed to look that up too11:00
olofkstekern: You're good with wishbone byte-select stuff. Any comments?11:06
stekernhmm, can you give a summary?11:07
stekernhaven't read the backlog today11:07
juliusb_stekern: whoops, that was meant for wallento!11:11
wallentoah, yeah, I think he also used reveal.js11:12
wallentoquite easy to use and publish11:12
heshamolofk: The vscale core issues the right address with the least significant two bits set to 00.
stekernreveal.js is nice, yeah11:12
heshamAnd then do the shift. This is the same as what a wishbone-interface does I think.11:13
stekernyes, on a 32-bit wishbone interface, the two lsb's are don't care11:14
heshamAnd they're used for setting sel bits right?11:15
stekernused where?11:16
stekerninside a wishbone master, they could be used to generate sel bits11:16
stekernif the wishbone master internally generates addresses with 8-bit granularity11:17
heshamstekern: Yes, from the vscale that acts as a wishbone master.11:51
olofkstekern: hesham's wb master generates byte accesses by setting sel = 0x1 and shifting the data 0, 8, 16 or 24 bis, if I have understood this correctly11:56
olofkBut my understanding of wb is that you don't shift the data, and instead set sel to 0x1, 0x2, 0x4 or ox811:56
stekernhow would the slave otherwise know what address you are trying to access?11:57
heshamolofk: OK, I can modify the vscale master core to comply with this behaviour. It's only the load instruction that behaves this way.13:37
andrzejrolofk, does wb spec require 2 lsbs to be 0 or is it just a common practice?13:58
andrzejrI am planning adding support for byte/half-word access to wb bfm. I assumed there is several ways to access the same address14:00
olofkandrzejr: I remember that we had a discussion about this a while ago, and I'm not sure, but I think the conclusion was that the 2 lsb had to be zero.14:02
andrzejrBTW, have you done any work on bfm recently? asking to avoid duplication of effort14:07
olofkhesham: So you mean that the sel mask is ok on writes?14:08
olofkandrzejr: No work done. Love to see some effort on the byte/half-word stuff14:09
heshamolofk: Yes14:09
heshamThere's no shifting from the vscale this14:09
heshamolofk: Could you double check please?
heshamDon't care about the half-word accesses for now, I fixed it on my local repo14:10
olofkhesham: How is dmem size defined? Is it the number of bytes to read/write?14:12
heshamYes 0 for byte accesses14:12
olofkok, and 1 for 16-bit, 2 for 32-bit?14:12
olofkI think that looks fine (for byte accesses)14:13
olofkNot sure about the endianness of course :)14:13
olofkMaybe it's 8 >> dmem_addr[1:0]14:13
olofkhmm.. is the sel mask generation the only thing that differs between a big-endian and little-endian master?14:14
heshamYeah, for half-word it would be "(dmem_size == 1 || dmem_size == 5)? 3 << (dmem_addr[1:0])"14:14
heshamolofk: That's what I think so far.14:15
heshamAnd it works fine with sb/sw with the srec loader14:15
heshamAnd hello world, bootloader14:16
olofkHave you tried regenerating with datawidth=8?14:17
olofkfor the uart slave14:17
heshamYeah, and it fails.14:18
olofkStill need to fix the endian selector there I guess14:39
heshamolofk: Let me try to fix things from the vscale master core first, and see if this issue can be handled there.14:47
heshamIt would a workaround, so it's better to parametrize endianness from the wb_data_resize instead14:48
olofkBut it would be good to know if it works with the workaround14:57
heshamolofk: I've been trying but that's a headache15:14
heshamIf I want a byte from the memory for example, I've to shift it all the time because it's placed on the wrong MSB instead of the LSB order.15:16
heshamFrom little endian perspective :/15:17
-!- _franck__ is now known as _franck_19:48
--- Log closed Sat Nov 14 00:00:09 2015

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