IRC logs for #openrisc Thursday, 2015-11-12

--- Log opened Thu Nov 12 00:00:06 2015
olofkHas anyone used ?09:51
heshamolofk: So picorv32 is working now, that's great! Would you like to try out the srec bootloader there?10:06
olofkhesham: Yeah. I fixed the elf-loader to handle little endian as well10:07
olofkThere's no UART on the picorv32 system, so I can't test the srec stuff10:07
heshamIs not it working with other open cores like mor1kx?10:08
heshamAnd how can I run/test it?10:08
heshamIf you're interested I can work on getting my vscale work integrated. But they the code is not very mature yet.10:09
olofkhesham: Ah, you wrote it in C?10:09
heshamNo assembly10:10
heshamIt's initializing the UART core, and just getting ascii srec file from PC, and jump to 0x20010:10
olofkThen it should work for the OpenRISC stuff too. Want to try it, but haven't got time right now. Is it small enough to fit into a boot ROM10:10
olofkAnd I would love to see your vscale stuff integrated, but no stress10:11
heshamIt won't work with OpenRISC because I wrote it in RISC-V assembly10:11
olofkaha. I got you wrong then10:12
heshamSo if I want to add the vscale stuff, would it be a new "systems/riscv" or a separate core?10:12
heshamwith definitions at orpsoc-defines.v?10:12
olofkI think it's better to use a new core.10:12
olofkHopefully it will get a little easier to build new systems in the future, so we don't have to mess with `ifdefs10:13
heshamAh, OK, I will try to add support to refer to my vscale repo like picorv3210:14
heshamThe bootloader is currently about 250 words10:14
hesham32-bit words, but it's not optimized at all.10:15
olofk250 words is ok. I still thought it was written in C when I asked about the size10:21
olofkhesham: If you're not ready to integrate vscale into orpsoc-cores, you can put a .core file in your repo, and I can just clone it and add it to the library path to test it10:22
olofkDo you have it in a public repo already?10:22
heshamolofk: Yes
heshamI would see what you did with picorv32, and try to imitate it there. And maybe add support for an entire system to be built from FuseSoC like with mor1kx-generic10:26
olofkhesham: Cool. I'll take a look when I get some time11:27
heshamolofk: OK, I've sometime today, so I'll try to add the support to my repos, and maybe push pull requests later.11:29
olofkhesham: Cool!11:33
olofkhesham: I started adding support for simulating the upstream vscale13:15
olofkSeems like it runs fine in icarus with my first test case at least13:15
heshamolofk: Great. Should I hold off my "systems/vscale-generic" addition?13:16
olofkhesham: It would be great to have a SoC built around vscale. I have just added stuff to simulate the CPU core13:18
heshamOk perfect. I'll test it. It boots from 0xf0000000 BTW.13:20
olofkThanks. I might need some help13:23
olofkhesham: Do you have any elf files I can use to test it? There's only hex files in the vscale repo, and I would like to change it to use the elf-loader instead13:24
heshamI have the bootloader for Icarus that just jumps to 0x200 as RISC-V expects13:25
heshamCurrently I'm using hello world, but this will need UART13:25
heshamI can write/compile an elf program for you, just let me know what do you need from it.13:25
olofkhesham: Great. I'll ping you when I need an elf14:01
heshamolofk: I submitted a pull request for a vscale-generic SoC that runs hello world14:13
heshamolofk: and sent you an e-mail with a hello world elf file to test with.14:29
olofkThanks hesham. I pulled the wb_riscvscale patch and commented on the other one14:43
heshamolofk: Thanks for the comments. I am working on them now14:55
heshamI get an error when changing orpsoc_tb.v to vscale_tb.v14:56
hesham"error: Unable to find the root module "orpsoc_tb" in the Verilog source."14:56
heshamwb_intercon assumes orpsoc_tb14:56
olofkhesham: Ah... that's not very well documented, and a bit hacky15:11
olofkYou need to add a section called [simulator] and add a entry "toplevel = name_of_toplevel_module"15:12
heshamSo should I keep it orpsoc_tb for now?15:12
heshamAh, that better15:12
olofkLike this
olofkActually, I think you can also run with --testbench=name_of_module15:13
heshamolofk: "error: Unable to find the root module "bench/verilog/vscale_tb.v" in the Verilog source."15:36
heshamAlthough it's there.15:37
heshamAh sorry, I should provide the module name not the file15:37
heshamIt works now15:37
heshamolofk: Check the pull request again please. I've addressed all your comments (I hope).16:52
olofkAnyone with vivado 2015.1 who can check if the clog2 bug is there?22:21
--- Log closed Fri Nov 13 00:00:07 2015

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