| --- Log opened Wed Nov 04 00:00:55 2015 | ||
| andrzejr | stekern, I wonder if we could have some debugging/monitor outputs available at the mor1kx top-level | 01:56 |
|---|---|---|
| andrzejr | signals like exception, sr, pc, exec_valid, instruction etc. Most of them are already available in mor1kx_cpu | 02:01 |
| stekern | andrzejr: there are already: https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx.v#L168 | 07:30 |
| andrzejr2 | stekern, yes, there are some indeed. my mistake. would be useful to have some flags to trigger on when debugging hw. | 13:18 |
| andrzejr2 | various exceptions etc | 13:19 |
| juliusb_ | hah: http://lkml.iu.edu/hypermail/linux/kernel/1510.3/02866.html | 14:22 |
| hesham | olofk: How was you going to send Hex/Intel format file over UART? | 16:59 |
| hesham | I mean from the PC part. Would you recommend an existing Linux package/program for doing so? | 17:02 |
| hesham | I'd try kermit | 17:07 |
| juliusb_ | https://github.com/nickg/nvc | 17:07 |
| juliusb_ | or, more interestingly: http://www.doof.me.uk/category/vhdl/ | 17:07 |
| salman_ | the I2C code in the fusesoc de0_nano seems not to have pullups enabled on the SDA and SCL lines in Altera..why not? | 17:18 |
| olofk | andrzejr: I think wallento has some debugging infrastructure that hooks up to the trace ports in mor1kx | 22:47 |
| andrzejr | hi olofk | 22:48 |
| andrzejr | for hw debug it is handy to have some strobe/flag signals available at the top level. At the moment I'm modifying mor1kx to dig out some signals of interest. | 22:49 |
| andrzejr | I gave up eth, too much work to set up a sim/test rig and I don't need eth that badly | 22:51 |
| andrzejr | (DDR was a different story) | 22:51 |
| andrzejr | _franck_, this issue is still present in 4.2: http://opencores.org/forum,OpenRISC,0,5444 | 23:40 |
| andrzejr | juliusb_, this is very interesting indeed. LLVM + "v-code" (an intermediate language) looks like the best solution for VHDL+Verilog+... simulation. Too bad he is targeting only VHDL. | 23:54 |
| andrzejr | maybe iverilog could be made to only emit v-code and leave the rest to nvc | 23:55 |
| --- Log closed Thu Nov 05 00:00:56 2015 | ||
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