IRC logs for #openrisc Wednesday, 2015-11-04

--- Log opened Wed Nov 04 00:00:55 2015
andrzejrstekern, I wonder if we could have some debugging/monitor outputs available at the mor1kx top-level01:56
andrzejrsignals like exception, sr, pc, exec_valid, instruction etc. Most of them are already available in mor1kx_cpu02:01
stekernandrzejr: there are already:
andrzejr2stekern, yes, there are some indeed. my mistake. would be useful to have some flags to trigger on when debugging hw.13:18
andrzejr2various exceptions etc13:19
heshamolofk: How was you going to send Hex/Intel format file over UART?16:59
heshamI mean from the PC part. Would you recommend an existing Linux package/program for doing so?17:02
heshamI'd try kermit17:07
juliusb_or, more interestingly:
salman_the I2C code in the fusesoc de0_nano seems not to have pullups enabled on the SDA and SCL lines in Altera..why not?17:18
olofkandrzejr: I think wallento has some debugging infrastructure that hooks up to the trace ports in mor1kx22:47
andrzejrhi olofk22:48
andrzejrfor hw debug it is handy to have some strobe/flag signals available at the top level. At the moment I'm modifying mor1kx to dig out some signals of interest.22:49
andrzejrI gave up eth, too much work to set up a sim/test rig and I don't need eth that badly22:51
andrzejr(DDR was a different story)22:51
andrzejr_franck_, this issue is still present in 4.2:,OpenRISC,0,544423:40
andrzejrjuliusb_, this is very interesting indeed. LLVM + "v-code" (an intermediate language) looks like the best solution for VHDL+Verilog+... simulation. Too bad he is targeting only VHDL.23:54
andrzejrmaybe iverilog could be made to only emit v-code and leave the rest to nvc23:55
--- Log closed Thu Nov 05 00:00:56 2015

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