IRC logs for #openrisc Tuesday, 2015-11-03

--- Log opened Tue Nov 03 00:00:53 2015
andrzejrHas anyone seen a RMII PHY model?08:33
andrzejrCan't fix the ethernet problems without building a proper simulation rig. The one in ethmac is pretty good but uses MII.08:41
andrzejrAnother question:08:53
wallentonoice08:53
wallentosorry, wrong chat ;)08:53
andrzejrhas anyone tested de0_nano or another working system with memory connected via wb arbiter? I've been seeing some weird (probably non-critical) issues like one master starving others during multiple wb bursts.08:56
latifhi all.. how much time it takes to obtain results for coremark app on openrisc..for 4000 iterations09:34
latifHi all, We have a problem running coremark app on orpsoc-v3. We are using the old coremark_portme.c, .h and .mak files.10:18
latifShould we change anything other than or32-elf-  -->  or1k-elf-?10:18
stekernlatif: I have coremark ports lying around somewhere that I can dig up10:35
stekernhttp://oompa.chokladfabriken.org/tmp/coremark-or1k/10:39
GeneralStupidandrzejr_: the de2 port uses wb_arbiter on SD RAM i guess11:12
latifstekern: thanks for reply.. are you also using coremarkv1 and atlys board with or1k-elf toolchain??11:13
stekernI've done that at some point, yes11:14
latifok. thanks again. I am trying..11:16
GeneralStupidAre there some diagrams or smthg. which i can use for my project documentatioN=11:54
latifstekern: your port is not working12:00
latifbecause i think there are some changes according to the toolchain12:00
latifsome of your descriptions are not avalieble rigth now.. like spr-defs.h and some macros defined in this codes12:01
latiflike.. SPR_TTCR12:01
stekernah, right...12:09
stekernlemme see if I have a newer one then12:09
latifok. please check it. thanks.12:11
stekerncan't find one, but you should be fine by just replacing those with the right ones12:12
GeneralStupidAnd please give me some advice or a link how to add custom instructions...12:20
olofkstekern: Welease mow1kx!21:22
mor1kx[mor1kx] skristiansson created mor1kx_v4 (+1 new commit): https://github.com/openrisc/mor1kx/commit/b8c1a18a77ca21:28
mor1kxmor1kx/mor1kx_v4 b8c1a18 Stefan Kristiansson: mor1kx_v4.121:28
mor1kx[mor1kx] skristiansson tagged v4.1 at mor1kx_v4: https://github.com/openrisc/mor1kx/commits/v4.121:28
olofk:)21:29
mor1kx[mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/69b97fcb43b35d6c6639ecc68e63d912c09ee8da21:30
mor1kxmor1kx/master 69b97fc Stefan Kristiansson: Bump version number to 5.021:30
olofkwoaahh... slow down!21:30
olofkmor1kx-4.1 is in orpsoc-cores now21:36
GeneralStupidolofk: wow :) Whats new?! :)21:40
olofkI guess the FPU is the big new thing, but stekern can give you more details22:14
heshamHi22:50
heshamAt the bootrom.S code here http://opencores.org/websvn,filedetails?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsw%2Fbootrom%2Fbootrom.S ...22:50
heshamWhat does the the first jump to spi_xfer from spi_init do?22:51
--- Log closed Wed Nov 04 00:00:55 2015

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