| --- Log opened Thu Oct 29 00:00:27 2015 | ||
| --- Day changed Thu Oct 29 2015 | ||
| _franck_ | andrzejr: in general, you get such information from the PHY device thru MDIO interface | 07:12 |
|---|---|---|
| stekern | true, but usually that information is then used to write some register in the MAC | 07:12 |
| stekern | and I'd rather just snoop that signal than snooping the mdio interface | 07:13 |
| stekern | (or read the mdio interface from hw) | 07:13 |
| stekern | that said, do you really care about 10mb? | 07:14 |
| _franck_ | stekern: does the MAC use the MDIO by itself ? I don't think so. I thaught the MAC was doing 10/100 depending on the incoming clock (at least in MII mode) | 07:18 |
| stekern | _franck_: hmm, yes, you're right, a register in the MAC only makes sense for RMII | 08:11 |
| stekern | so either, 1) make your rmii-mii converter configurable (e.g. with wb interface) | 08:12 |
| stekern | or 2) snoop the mdio bus | 08:12 |
| stekern | for 2), this might be of help: https://github.com/skristiansson/orpsoc-cores/blob/multicore/cores/mac2mac_bridge/rtl/verilog/mac2mac_mdio.v | 08:18 |
| stekern | it's a fake ksz8041 phy ;) | 08:19 |
| andrzejr | interesting. Do I understand correctly that CPU has to request the read from MDIO status register for (2) to work? I wonder if that works with existing drivers. | 08:32 |
| andrzejr | (1) is simpler but needs changes to the drivers. | 08:33 |
| stekern | yes | 08:35 |
| stekern | I would suggest to do 1 and default to 100MB | 08:36 |
| stekern | Mb | 08:37 |
| stekern | that way it'll work 99.9% of the times without driver changes too :) | 08:37 |
| andrzejr | another question - do I need a FIFO + elastic buffer in the mii2rmii Rx? LAN8720A PHY already includes such buffer (it has to - it gets a fixed clock from rmii) | 08:38 |
| stekern | I think that might be a good idea, yes | 08:38 |
| andrzejr | will do (1) then, seems simpler. | 08:39 |
| andrzejr | stekern, how do you verify your mii bridge, do you have any testbenches or bfms? | 08:40 |
| stekern | you could probably get away with just adding syncronizers between the clocks though | 08:40 |
| stekern | you mean for: https://github.com/skristiansson/orpsoc-cores/blob/multicore/cores/mac2mac_bridge/rtl/verilog/mac2mac_bridge.v | 08:42 |
| stekern | nah, it's just connecting signals together | 08:42 |
| andrzejr | You mean the FIFO is just needed for timing closure between PHY and rmii Rx? | 08:42 |
| stekern | yes | 08:43 |
| stekern | data rate is of course always the same | 08:43 |
| andrzejr | I used to do in the past that but that was in an interface clocked at 500MHz. Seem like a good idea if we are uncertain about timing at the output of the PHY | 08:44 |
| andrzejr | gtg, thank you for help | 08:45 |
| jkent | anyone around familiar with the DE1 fusesoc system configuration? i'd like to get some sort of hello word program running... either blinking an led or something over uart... i've been able to build and program and load code, but nothing i've done has given me indication that the core is executing code | 20:04 |
| GeneralStupid | Hi, are you using openocd? | 20:11 |
| GeneralStupid | you can halt and check with reg npc if the npc changes from 0x?100 :) | 20:11 |
| GeneralStupid | jkent: | 20:12 |
| jkent | yes, i was.. i'll give that a shot | 20:15 |
| jkent | okay, npc does change | 21:29 |
| olofk | jkent: GeneralStupid had the same situation just some days ago | 21:33 |
| olofk | What version of openocd are you using? | 21:34 |
| jkent | Open On-Chip Debugger 0.10.0-dev-00044-g3edb157 (2015-10-24-02:12) | 21:34 |
| jkent | compiled myself | 21:34 |
| olofk | Can you verify that the reset is released? By for example connect it to a led | 21:34 |
| jkent | oh, i did say npc /does/ change, so code should be executing | 21:34 |
| olofk | oh sorry | 21:35 |
| jkent | my problem is likely code that does not match the hardware configuration, at least thats my guess at the moment | 21:36 |
| olofk | You used a simple hello world, right? Can you see where npc ends up? | 21:38 |
| jkent | i have previously.. currently i'm using the orconf2013 timerled binary for the de0_nano... let me try that again to be sure, its been a few days since i've touched this | 21:40 |
| jkent | npc ends up at 0x228 | 21:44 |
| jkent | no output, and did not see the tx led on my DE1 board flash | 21:45 |
| olofk | Hmm.. that's a bus error | 21:45 |
| olofk | Which might mean that there is something wrong with the connections on the wishbone bus. Did you change anything in your port? | 21:45 |
| jkent | did not, its exactly as is from git | 21:46 |
| olofk | hmm.. got to go now, but I'll try to think of ideas to debug this | 21:47 |
| jkent | thank you, much appreciated :) | 21:47 |
| olofk | Just thought of something. I think there is a register that contains the address that was executed just before jumping to 0x200. Can't remember which one though | 21:50 |
| _franck_ | jkent: I have a barebox support for de1 here: https://github.com/fjullien/barebox | 22:16 |
| GeneralStupid | jkent: hey, how is it configured from git? | 22:30 |
| GeneralStupid | jkent: how do you know your LED addresses? | 22:30 |
| jkent | _franck_: pc stops at 0x7CC with barebox | 22:34 |
| GeneralStupid | jkent: can we see the code? | 22:34 |
| jkent | GeneralStupid: re configured from git and led addresses: its from git as-is, i haven't made any changes... don't know addresses of things yet, i haven't dug into the hardware configuration yet | 22:36 |
| jkent | hello world program was just a printf, nothing fancy... newlib sets up the uart by default, right? | 22:36 |
| GeneralStupid | jkent: printf did not work for me either... | 22:37 |
| _franck_ | jkent: yes it does. I'll send you an led blink for you to try | 22:37 |
| jkent | _franck_: thank you! | 22:39 |
| _franck_ | jkent: https://drive.google.com/file/d/0B3Ee4BAXlAOhT3ozVDYxWS1fX00/view?usp=sharing | 22:39 |
| _franck_ | jkent: I'm very suprised it doesn't work. I have used de1 a lot | 22:40 |
| jkent | I've got one of the older boards, before terasic started putting lower spec parts on them, so i'm supprised stuff isn't working either | 22:41 |
| _franck_ | https://github.com/openrisc/orpsoc-cores/blob/master/systems/de1/rtl/verilog/include/orpsoc-defines.v#L38 | 22:43 |
| _franck_ | ^ change this define from OR1200_CPU to MOR1KX_CPU | 22:43 |
| _franck_ | I should commit this change. or1200 shouldn't be used anymore | 22:44 |
| jkent | hmm, no blink, i was supposed to set npc to 0x100 before resume, correct? npc is at 0x104 | 22:45 |
| GeneralStupid | yes | 22:46 |
| GeneralStupid | _franck_: i already removed it from "my" de2 port | 22:46 |
| jkent | i'll make that change | 22:46 |
| _franck_ | jkent: GeneralStupid : you can also use https://github.com/openrisc/or1k-tcltools to download your files | 22:47 |
| _franck_ | I'll try to give de1 a try tommorow | 22:48 |
| GeneralStupid | _franck_: looks nice. help for debugging? | 22:49 |
| _franck_ | I did this before we got support in openocd | 22:50 |
| _franck_ | was used to download and execute program. However, it's a bit slow | 22:51 |
| _franck_ | plus you can use it at the same time you use signal tap | 22:52 |
| GeneralStupid | yes that signal tap thing... | 22:53 |
| GeneralStupid | I need something where i can test vhdl stuff mixed with the mor1kx :) | 22:53 |
| GeneralStupid | I dislike that you need to write so many things twice in vhdl but verilog is so cryptic for me | 22:54 |
| jkent | neat, mor1kx gets a faster Fmax | 22:55 |
| jkent | now npc is at 0xFC when i halt, with mor1kx | 22:58 |
| jkent | i do know my de1 is okay -- i'm able to run gary becker's coco3fpga project with zero issues | 22:59 |
| _franck_ | well I don't have more clue. I'll tell you tomorow when I try it | 23:02 |
| jkent | okay, your help is greatly appreciated :) | 23:02 |
| jkent | i would dig in deeper, but i don't know where to even begin at this point | 23:06 |
| andrzejr | olofk, how to build a system containing a core written in vhdl? | 23:34 |
| andrzejr | putting rtl source files in [verilog] "almost" works, but ise complains that submodules are not found in a compiled library. | 23:41 |
| andrzejr | "Cannot find <a_submodule> in library <a_vhdl_library>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file." | 23:42 |
| _franck_ | andrzejr: https://github.com/openrisc/orpsoc-cores/blob/master/systems/neek/neek.core#L31 | 23:42 |
| andrzejr | _franck_, thanks. I tried that as well and I get another error. Not sure if 'ise' backend recognizes [vhdl] section at all | 23:44 |
| _franck_ | ah, yes it may be supported by quartus only. Should not be hard to add. | 23:45 |
| _franck_ | bed time, gn | 23:46 |
| --- Log closed Fri Oct 30 00:00:48 2015 | ||
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