IRC logs for #openrisc Thursday, 2015-10-29

--- Log opened Thu Oct 29 00:00:27 2015
--- Day changed Thu Oct 29 2015
_franck_andrzejr: in general, you get such information from the PHY device thru MDIO interface07:12
stekerntrue, but usually that information is then used to write some register in the MAC07:12
stekernand I'd rather just snoop that signal than snooping the mdio interface07:13
stekern(or read the mdio interface from hw)07:13
stekernthat said, do you really care about 10mb?07:14
_franck_stekern: does the MAC use the MDIO by itself ? I don't think so. I thaught the MAC was doing 10/100 depending on the incoming clock (at least in MII mode)07:18
stekern_franck_: hmm, yes, you're right, a register in the MAC only makes sense for RMII08:11
stekernso either, 1) make your rmii-mii converter configurable (e.g. with wb interface)08:12
stekernor 2) snoop the mdio bus08:12
stekernfor 2), this might be of help:
stekernit's a fake ksz8041 phy ;)08:19
andrzejrinteresting. Do I understand correctly that CPU has to request the read from MDIO status register for (2) to work? I wonder if that works with existing drivers.08:32
andrzejr(1) is simpler but needs changes to the drivers.08:33
stekernI would suggest to do 1 and default to 100MB08:36
stekernthat way it'll work 99.9% of the times without driver changes too :)08:37
andrzejranother question - do I need a FIFO + elastic buffer in the mii2rmii Rx? LAN8720A PHY already includes such buffer (it has to - it gets a fixed clock from rmii)08:38
stekernI think that might be a good idea, yes08:38
andrzejrwill do (1) then, seems simpler.08:39
andrzejrstekern, how do you verify your mii bridge, do you have any testbenches or bfms?08:40
stekernyou could probably get away with just adding syncronizers between the clocks though08:40
stekernyou mean for:
stekernnah, it's just connecting signals together08:42
andrzejrYou mean the FIFO is just needed for timing closure between PHY and rmii Rx?08:42
stekerndata rate is of course always the same08:43
andrzejrI used to do in the past that but that was in an interface clocked at 500MHz. Seem like a good idea if we are uncertain about timing at the output of the PHY08:44
andrzejrgtg, thank you for help08:45
jkentanyone around familiar with the DE1 fusesoc system configuration?  i'd like to get some sort of hello word program running... either blinking an led or something over uart... i've been able to build and program and load code, but nothing i've done has given me indication that the core is executing code20:04
GeneralStupidHi, are you using openocd?20:11
GeneralStupidyou can halt and check with reg npc if the npc changes from 0x?100 :)20:11
jkentyes, i was.. i'll give that a shot20:15
jkentokay, npc does change21:29
olofkjkent: GeneralStupid had the same situation just some days ago21:33
olofkWhat version of openocd are you using?21:34
jkentOpen On-Chip Debugger 0.10.0-dev-00044-g3edb157 (2015-10-24-02:12)21:34
jkentcompiled myself21:34
olofkCan you verify that the reset is released? By for example connect it to a led21:34
jkentoh, i did say npc /does/ change, so code should be executing21:34
olofkoh sorry21:35
jkentmy problem is likely code that does not match the hardware configuration, at least thats my guess at the moment21:36
olofkYou used a simple hello world, right? Can you see where npc ends up?21:38
jkenti have previously.. currently i'm using the orconf2013 timerled binary for the de0_nano... let me try that again to be sure, its been a few days since i've touched this21:40
jkentnpc ends up at 0x22821:44
jkentno output, and did not see the tx led on my DE1 board flash21:45
olofkHmm.. that's a bus error21:45
olofkWhich might mean that there is something wrong with the connections on the wishbone bus. Did you change anything in your port?21:45
jkentdid not, its exactly as is from git21:46
olofkhmm.. got to go now, but I'll try to think of ideas to debug this21:47
jkentthank you, much appreciated :)21:47
olofkJust thought of something. I think there is a register that contains the address that was executed just before jumping to 0x200. Can't remember which one though21:50
_franck_jkent: I have a barebox support for de1 here:
GeneralStupidjkent: hey, how is it configured from git?22:30
GeneralStupidjkent: how do you know your LED addresses?22:30
jkent_franck_: pc stops at 0x7CC with barebox22:34
GeneralStupidjkent: can we see the code?22:34
jkentGeneralStupid: re configured from git and led addresses: its from git as-is, i haven't made any changes... don't know addresses of things yet, i haven't dug into the hardware configuration yet22:36
jkenthello world program was just a printf, nothing fancy... newlib sets up the uart by default, right?22:36
GeneralStupidjkent: printf did not work for me either...22:37
_franck_jkent: yes it does. I'll send you an led blink for you to try22:37
jkent_franck_: thank you!22:39
_franck_jkent: I'm very suprised it doesn't work. I have used de1 a lot22:40
jkentI've got one of the older boards, before terasic started putting lower spec parts on them, so i'm supprised stuff isn't working either22:41
_franck_^ change this define from OR1200_CPU to MOR1KX_CPU22:43
_franck_I should commit this change. or1200 shouldn't be used anymore22:44
jkenthmm, no blink, i was supposed to set npc to 0x100 before resume, correct?  npc is at 0x10422:45
GeneralStupid_franck_: i already removed it from "my" de2 port22:46
jkenti'll make that change22:46
_franck_jkent: GeneralStupid : you can also use to download your files22:47
_franck_I'll try to give de1 a try tommorow22:48
GeneralStupid_franck_: looks nice. help for debugging?22:49
_franck_I did this before we got support in openocd22:50
_franck_was used to download and execute program. However, it's a bit slow22:51
_franck_plus you can use it at the same time you use signal tap22:52
GeneralStupidyes that signal tap thing...22:53
GeneralStupidI need something where i can test vhdl stuff mixed with the mor1kx :)22:53
GeneralStupidI dislike that you need to write so many things twice in vhdl but verilog is so cryptic for me22:54
jkentneat, mor1kx gets a faster Fmax22:55
jkentnow npc is at 0xFC when i halt, with mor1kx22:58
jkenti do know my de1 is okay -- i'm able to run gary becker's coco3fpga project with zero issues22:59
_franck_well I don't have more clue. I'll tell you tomorow when I try it23:02
jkentokay, your help is greatly appreciated :)23:02
jkenti would dig in deeper, but i don't know where to even begin at this point23:06
andrzejrolofk, how to build a system containing a core written in vhdl?23:34
andrzejrputting rtl source files in [verilog] "almost" works, but ise complains that submodules are not found in a compiled library.23:41
andrzejr"Cannot find <a_submodule> in library <a_vhdl_library>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file."23:42
andrzejr_franck_, thanks. I tried that as well and I get another error. Not sure if 'ise' backend recognizes [vhdl] section at all23:44
_franck_ah, yes it may be supported by quartus only. Should not be hard to add.23:45
_franck_bed time, gn23:46
--- Log closed Fri Oct 30 00:00:48 2015

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