| --- Log opened Wed Oct 28 00:00:45 2015 | ||
| stekern | juliusb_: I see that your fellow countrymen do some quality research: http://www.ncbi.nlm.nih.gov/pmc/articles/PMC1322240/ | 06:18 |
|---|---|---|
| poke53281 | Lol, that's called quality research nowadays ;) | 10:30 |
| poke53281 | Might be a candidate for the IG Nobel Price. | 10:30 |
| juliusb_ | haha, great stuff | 10:37 |
| juliusb_ | perhaps they were motivated to do the study by the lack of teaspoons around their workplace | 10:37 |
| poke53281 | Yeah I have to admit, that the teaspoon loss is also a problem here. | 10:39 |
| poke53281 | Wormholes in the dishwasher is my theory. | 10:40 |
| hesham | Would anyone be interested in a wishbone compliant RISC-V core? | 16:02 |
| wallento | another risc-v core dealer ;) | 16:02 |
| hesham | I got one RISC-V/Vscale working instead of the mor1kx, it runs on icarus, | 16:02 |
| wallento | cool | 16:02 |
| hesham | No, I just used the existing vscale core | 16:03 |
| hesham | And got rid of their nasti/hasti HTIF stuff | 16:03 |
| hesham | A simple assembly hello world working their with UART, | 16:04 |
| wallento | cool, did you already put it somewhere? | 16:08 |
| hesham | wallento: Not yet, I guess it would be easy to be maintained within fusesoc, and build from their | 16:11 |
| hesham | wallento: The UART doesn't have to be initialized on Icarus to print out some data, does it have to be initialized when the actual uart16550 core runs on FPGA? | 16:13 |
| wallento | it needs to be configured | 16:13 |
| wallento | clock divisor | 16:14 |
| wallento | and interrupts | 16:14 |
| hesham | Yeah, I did it for RTEMS | 16:14 |
| wallento | like this: https://github.com/wallento/newlib-cygwin/blob/master/libgloss/or1k/or1k_uart.c#L109 | 16:14 |
| wallento | ah, okay, right | 16:14 |
| hesham | I think I'll have to write the UART init stuff for RISC-V again to get it running ot Atlys | 16:14 |
| hesham | Or just copy it from libgloss or RTEMS since it's mostly C code. | 16:15 |
| olofk | hesham: Great stuff. I have wanted to have a RISC-V core running with FuseSoC | 17:57 |
| olofk | And if you make it wb, we could reuse most of the infrastructure. Happy to help out | 17:57 |
| hesham | olofk: Yes, and even with the FPGA boards | 17:59 |
| hesham | When it's mature enough, should I make a pull request to your FuseSoC? | 18:01 |
| olofk | hesham: Sure, or orpsoc-cores to be exact | 18:02 |
| olofk | Still want to rename that repo at some point | 18:02 |
| hesham | I guess I'll have to create a separate repo for wb_vscale repo first | 18:02 |
| olofk | Should have done it years ago | 18:02 |
| olofk | Yeah, you can do that, and just add the path to your repo to fusesoc.conf | 18:02 |
| hesham | But I guess if I need some command line like" "fusesoc sim --force riscv-generic --elf-load=start.elf --vcd" | 18:03 |
| hesham | I would have to do some coding with FuseSoC | 18:03 |
| olofk | You don't need force anymore actually | 18:03 |
| hesham | Right? | 18:04 |
| olofk | But the rest is correct, given that you have a memory that supports --elf-load | 18:04 |
| hesham | Well, that's how I got hello world working on Icarus | 18:04 |
| olofk | ah ok | 18:04 |
| olofk | cool | 18:05 |
| olofk | Well, that's really nice | 18:05 |
| hesham | Ah, I had to change some stuff with vpi/elf code | 18:05 |
| hesham | Byte ordering... | 18:05 |
| olofk | ahh.. | 18:05 |
| hesham | or1k is big endian right? | 18:05 |
| olofk | yep | 18:05 |
| olofk | I wonder if that can be automated somehow | 18:06 |
| hesham | I made it elf loader little one | 18:06 |
| hesham | Maybe some #ifdef for now | 18:06 |
| hesham | RISCV vs OR1K? | 18:06 |
| olofk | Yeah, but I'm thinking of how to set this in the top-level | 18:06 |
| olofk | Is there information about endianness in the elf itself? | 18:07 |
| hesham | Yeah, I am not sure yet how the whole thing would be integrated. | 18:07 |
| hesham | The elf header should define that I guess | 18:07 |
| hesham | That makes more sense | 18:07 |
| hesham | So the elfloader should check for the ABI and decide what to do then | 18:08 |
| olofk | Exactly | 18:08 |
| hesham | Ok | 18:09 |
| hesham | Have you managed to get FPGA elf loader yet? | 18:09 |
| olofk | Not over UART | 18:10 |
| hesham | Ah ok. | 18:11 |
| olofk | I turned out that I suck at asm programming nowadays :) | 18:11 |
| hesham | I guess I can live with the bootrom/spi for now | 18:12 |
| hesham | BTW, I was trying to get the MIG/DDR2 working as a separate core on Atlys board | 18:13 |
| hesham | I figured out that there are two DDR2 chips versions with shipped with Atlys | 18:13 |
| olofk | ahh. | 18:13 |
| hesham | The older one is micro and the newer is mira | 18:13 |
| olofk | Are they any different? | 18:14 |
| hesham | I wanted to ask you :) | 18:14 |
| hesham | I googled that | 18:14 |
| hesham | And the memory type is different when you're using the MIG tool | 18:14 |
| hesham | or1k is using the older Micron MT47H64M16-25E | 18:16 |
| olofk | Hmm.. hopefully they are equivalent, but I don't have a clue really | 18:17 |
| olofk | gtg | 18:17 |
| hesham | The Atlys manual states that the MIG should generate DDR2 with EDE1116AXXX-8E type for newer MIRA ones | 18:17 |
| olofk | I found a verilog model for the Elpida memory, but just like winbond they only supply encrypted verilog. | 21:23 |
| olofk | Is only Micron bright enough to actually supply usable memory models? | 21:24 |
| olofk | Doesn't seem like Miron chose to open up the models after acquiring Elpida | 21:25 |
| andrzejr | olofk, why don't you use Micron models then? | 21:27 |
| * andrzejr is checking the log | 21:29 | |
| andrzejr | hesham, my Nexys4DDR board uses a mira part too. Works with Micron model (as advised in the board manual) | 21:31 |
| olofk | andrzejr: ah cool. I actually used the micron model for the winbond part too. It's standard ddr2, so it should work | 21:32 |
| andrzejr | Not sure if timing information is correct though, there is no publicly available datasheet. The clock rate looks lower than advertised (200MHz vs 266MHz) | 21:32 |
| hesham | andrzejr: I tried to get it working (on ISE) outside FuseSoC, but got no luck. | 21:33 |
| hesham | I guess the Micron IP works with Mira too, since RTEMS can on or1k/fusesoc with the micron IP. | 21:34 |
| olofk | Would be nice to have a testbench for the atlys board | 21:35 |
| hesham | And the Atlys manual advises to use different memory type when building ddr2 ip for mira. | 21:35 |
| olofk | Even though it might make sense to have a functional model of the DDR2 controller instead since it's really slow to simulate the ddr2 model | 21:35 |
| olofk | oh well. Time to sleep now | 21:36 |
| hesham | night | 21:36 |
| andrzejr | I wrote a simple bfm for Xilinx DDR2 i/f to avoid issues with encrypted SERDES models. Works fine for simulating the system startup in icarus. | 21:40 |
| hesham | Ah, that's what I am working with for now, bfm on Icarus. | 22:01 |
| andrzejr | is there any way of getting the negotiated ethernet speed (10M or 100M) from ethmac? I need it for my mii2rmii adapter to produce a correct clock frequency for ethmac. | 23:23 |
| --- Log closed Thu Oct 29 00:00:27 2015 | ||
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