IRC logs for #openrisc Wednesday, 2015-10-28

--- Log opened Wed Oct 28 00:00:45 2015
stekernjuliusb_: I see that your fellow countrymen do some quality research:
poke53281Lol, that's called quality research nowadays ;)10:30
poke53281Might be a candidate for the IG Nobel Price.10:30
juliusb_haha, great stuff10:37
juliusb_perhaps they were motivated to do the study by the lack of teaspoons around their workplace10:37
poke53281Yeah I have to admit, that the teaspoon loss is also a problem here.10:39
poke53281Wormholes in the dishwasher is my theory.10:40
heshamWould anyone be interested in a wishbone compliant RISC-V core?16:02
wallentoanother risc-v core dealer ;)16:02
heshamI got one RISC-V/Vscale working instead of the mor1kx, it runs on icarus,16:02
heshamNo, I just used the existing vscale core16:03
heshamAnd got rid of their nasti/hasti HTIF stuff16:03
heshamA simple assembly hello world working their with UART,16:04
wallentocool, did you already put it somewhere?16:08
heshamwallento: Not yet, I guess it would be easy to be maintained within fusesoc, and build from their16:11
heshamwallento: The UART doesn't have to be initialized on Icarus to print out some data, does it have to be initialized when the actual uart16550 core runs on FPGA?16:13
wallentoit needs to be configured16:13
wallentoclock divisor16:14
wallentoand interrupts16:14
heshamYeah, I did it for RTEMS16:14
wallentolike this:
wallentoah, okay, right16:14
heshamI think I'll have to write the UART init stuff for RISC-V again to get it running ot Atlys16:14
heshamOr just copy it from libgloss or RTEMS since it's mostly C code.16:15
olofkhesham: Great stuff. I have wanted to have a RISC-V core running with FuseSoC17:57
olofkAnd if you make it wb, we could reuse most of the infrastructure. Happy to help out17:57
heshamolofk: Yes, and even with the FPGA boards17:59
heshamWhen it's mature enough, should I make a pull request to your FuseSoC?18:01
olofkhesham: Sure, or orpsoc-cores to be exact18:02
olofkStill want to rename that repo at some point18:02
heshamI guess I'll have to create a separate repo for wb_vscale repo first18:02
olofkShould have done it years ago18:02
olofkYeah, you can do that, and just add the path to your repo to fusesoc.conf18:02
heshamBut I guess if I need some command line like" "fusesoc sim --force riscv-generic --elf-load=start.elf --vcd"18:03
heshamI would have to do some coding with FuseSoC18:03
olofkYou don't need force anymore actually18:03
olofkBut the rest is correct, given that you have a memory that supports --elf-load18:04
heshamWell, that's how I got hello world working on Icarus18:04
olofkah ok18:04
olofkWell, that's really nice18:05
heshamAh, I had to change some stuff with vpi/elf code18:05
heshamByte ordering...18:05
heshamor1k is big endian right?18:05
olofkI wonder if that can be automated somehow18:06
heshamI made it elf loader little one18:06
heshamMaybe some #ifdef for now18:06
heshamRISCV vs OR1K?18:06
olofkYeah, but I'm thinking of how to set this in the top-level18:06
olofkIs there information about endianness in the elf itself?18:07
heshamYeah, I am not sure yet how the whole thing would be integrated.18:07
heshamThe elf header should define that I guess18:07
heshamThat makes more sense18:07
heshamSo the elfloader should check for the ABI and decide what to do then18:08
heshamHave you managed to get FPGA elf loader yet?18:09
olofkNot over UART18:10
heshamAh ok.18:11
olofkI turned out that I suck at asm programming nowadays :)18:11
heshamI guess I can live with the bootrom/spi for now18:12
heshamBTW, I was trying to get the MIG/DDR2 working as a separate core on Atlys board18:13
heshamI figured out that there are two DDR2 chips versions with shipped with Atlys18:13
heshamThe older one is micro and the newer is mira18:13
olofkAre they any different?18:14
heshamI wanted to ask you :)18:14
heshamI googled that18:14
heshamAnd the memory type is different when you're using the MIG tool18:14
heshamor1k is using the older Micron MT47H64M16-25E18:16
olofkHmm.. hopefully they are equivalent, but I don't have a clue really18:17
heshamThe Atlys manual states that the MIG should generate DDR2 with EDE1116AXXX-8E type for newer MIRA ones18:17
olofkI found a verilog model for the Elpida memory, but just like winbond they only supply encrypted verilog.21:23
olofkIs only Micron bright enough to actually supply usable memory models?21:24
olofkDoesn't seem like Miron chose to open up the models after acquiring Elpida21:25
andrzejrolofk, why don't you use Micron models then?21:27
* andrzejr is checking the log21:29
andrzejrhesham, my Nexys4DDR board uses a mira part too. Works with Micron model (as advised in the board manual)21:31
olofkandrzejr: ah cool. I actually used the micron model for the winbond part too. It's standard ddr2, so it should work21:32
andrzejrNot sure if timing information is correct though, there is no publicly available datasheet. The clock rate looks lower than advertised (200MHz vs 266MHz)21:32
heshamandrzejr: I tried to get it working (on ISE) outside FuseSoC, but got no luck.21:33
heshamI guess the Micron IP works with Mira too, since RTEMS can on or1k/fusesoc with the micron IP.21:34
olofkWould be nice to have a testbench for the atlys board21:35
heshamAnd the Atlys manual advises to use different memory type when building ddr2 ip for mira.21:35
olofkEven though it might make sense to have a functional model of the DDR2 controller instead since it's really slow to simulate the ddr2 model21:35
olofkoh well. Time to sleep now21:36
andrzejrI wrote a simple bfm for Xilinx DDR2 i/f to avoid issues with encrypted SERDES models. Works fine for simulating the system startup in icarus.21:40
heshamAh, that's what I am working with for now, bfm on Icarus.22:01
andrzejris there any way of getting the negotiated ethernet speed (10M or 100M) from ethmac? I need it for my mii2rmii adapter to produce a correct clock frequency for ethmac.23:23
--- Log closed Thu Oct 29 00:00:27 2015

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