| --- Log opened Sun Oct 25 00:00:40 2015 | ||
| -!- knz_ is now known as knz | 08:30 | |
| GeneralStupid | hi anyone here? | 09:19 |
|---|---|---|
| GeneralStupid | Is there any vhdl example how to "connect" to the wishbone bus? | 09:20 |
| olofk | GeneralStupid: Great news that you got it working | 10:35 |
| olofk | The size parameter in wb_intercon.conf just says how large address space to allocate for the core. | 10:36 |
| olofk | So for example if you set offset=0x90000000 and size=32 for the UART, all addresses from 0x90000000 to 0x9000001f will be routed to the UART core | 10:37 |
| GeneralStupid | olofk: thats what i thought... So i may could control the lcd with 8 bits because it cannot display 256 characters but it is easier to use 10 bits (or 16...) | 10:38 |
| olofk | GeneralStupid: It sounds like you want to set the datawidth parameter then | 10:39 |
| olofk | I think only 8 and 32 bits are supported right now, but andrzejr has a patch for 16 bits | 10:40 |
| GeneralStupid | olofk: yes... of course... | 10:40 |
| olofk | jkent: Could you send over the error log? I haven't tried building it in a while so maybe something is broke | 10:40 |
| GeneralStupid | so size=2 means? | 10:40 |
| olofk | The address space is two bytes, meaning that only address offset and offset+1 goes to the core | 10:41 |
| olofk | This is used for the gpio core since it only has two one-byte registers | 10:41 |
| GeneralStupid | but two bytes would be enogh for width 16, too or am i wrong? | 10:41 |
| olofk | In the rtl code datawidth determines the width of the of the wb_dat_* ports, and size sets the width of the wb_adr port | 10:42 |
| GeneralStupid | okay | 10:43 |
| GeneralStupid | but i need some informations about the wb bus :) | 10:43 |
| olofk | What kind of info? | 10:43 |
| GeneralStupid | iam not really into verilog, at work we use vhdl :) So how do i connect a new component with that bus?! | 10:44 |
| GeneralStupid | What do i have to take care of?! | 10:45 |
| olofk | andrzejr: That's excellent news! I'm really keen on rewriting the wishbone BFM in cocotb or similar to make it easier to catch more corner cases for bursting | 10:45 |
| GeneralStupid | it would have been easier to just calculate something in hardware and send an interrupt if it is finished :) | 10:47 |
| olofk | GeneralStupid: There are plenty of examples of wishbone slaves written in VHDL. The i2c component for example has both an VHDL and verilog example | 10:47 |
| olofk | And you should probably read the wishbone spec as well | 10:48 |
| olofk | But it's all quite simple for single accesses | 10:48 |
| olofk | when stb and cyc are both asserted, you look at adr to determine the requested address, we to see if it was a read or write request and wb_dat_i to get the data if it was a write | 10:49 |
| olofk | You then assert ack to notify the master that you have taken care of the request, and for reads you return the data in wb_dat_o at the same time | 10:49 |
| olofk | No need to worry about cti, bte, err, rty at this point | 10:49 |
| GeneralStupid | sounds okay :) | 10:50 |
| olofk | oh.. and if you use data ports that are wider than 8 bits you also need to check sel. | 10:50 |
| GeneralStupid | :/ | 10:50 |
| GeneralStupid | i thought databus would get to 15 downto 0 and thats it :) | 10:53 |
| olofk | If you only do 16-bit accesses to the core, you don't need to handle sel | 10:54 |
| GeneralStupid | i just want to put 16 bits from my binary to my lcd stuff (for the first, simple example...) | 10:56 |
| GeneralStupid | i need to show that tomorrow, but the npc problem ... | 10:56 |
| GeneralStupid | the next thing i want to try is some hardware calculations... i don't exactly know how to do this the best way (my experience: it depends on what i want to calculate) | 10:58 |
| GeneralStupid | but that gets important if iam ready with that lcd ... | 10:59 |
| GeneralStupid | olofk: do you use an generator for some hdl stuff? | 11:00 |
| olofk | GeneralStupid: Yes, in some cases. The wishbone interconnect is generated | 11:07 |
| olofk | And I have made some slave generators in the past, but nothing for wishbone | 11:07 |
| olofk | And I'm looking at generating top-levels from IP-Xact descriptions | 11:08 |
| jkent | olofk: did you want to see more than the failing link? http://pastebin.com/JdSpMsLw | 11:12 |
| olofk | jkent: I was mostly hoping to see some error message that I recognized, but this isn't my strongest side, so I'm afraid I can't help you much with it :/ | 11:16 |
| GeneralStupid | olofk: yeah, thats what you told a time ago... i hate that hdl is so redundant | 11:17 |
| olofk | jkent: Perhaps try --disable-sim. I don't think you need that | 11:17 |
| jkent | olofk: okay, i'll give that a go | 11:18 |
| olofk | A shot in the dark, but since the errors seems to come from libsim it's worth a shot | 11:18 |
| jkent | i'll show the waring with gas when i come to it | 11:18 |
| jkent | well, error, because of -Werror | 11:18 |
| olofk | cool. These things always need to be adjusted for newer versions of glibc and gcc | 11:18 |
| jkent | -Werror=unused-value: http://pastebin.com/mid1Ug39 | 11:24 |
| jkent | olofk: --disable-sim did the trick, it linked | 11:28 |
| jkent | thank you! | 11:28 |
| GeneralStupid | i think i should do more verilog stuff... it looks much less to write | 11:29 |
| GeneralStupid | vhdl gives you the feeling that you program something :) verilog looks a bit strange to me (always?!) | 11:32 |
| GeneralStupid | olofk: why should wb_adr_i == 0 if i want to output data?! | 11:49 |
| GeneralStupid | olofk: input, sorry input :) | 11:49 |
| GeneralStupid | input wb_adr_i == 1; output wb_adr_i == 0... I think i get it | 11:50 |
| GeneralStupid | wait a minute, it looks like it is not very complicated actually :) | 11:52 |
| andrzejr | olofk, not sure if better coverage would help here - in the simulation the output from the ddr2 controller behaves "as expected". I wonder if that has something to do with use of distributed RAM for caching in the xilinx code. | 12:10 |
| andrzejr | it looks like there is another bug in the code, because after fixing the first one I still get a bus error, just a bit later. When I simply disabled bursting support in my code (yes, I should have tried it a month ago) memory just works. | 12:13 |
| andrzejr | not sure about that random freeze when booting linux. I've got it twice yesterday but wasn't able to reproduce it since. | 12:16 |
| GeneralStupid | olofk: i think i got it... i dont need size = 2, i need size = 1 | 17:21 |
| GeneralStupid | and then i just put my LCD module and map it ... | 17:21 |
| GeneralStupid | olofk: is there a way to simulate this? | 17:22 |
| GeneralStupid | can anyone tell me how to access the output with newlib? | 18:09 |
| _franck_ | GeneralStupid: use pointer, something like *(uint8_t *)0x92000000 = 0x11 | 18:18 |
| GeneralStupid | _franck_: i have 0x94000000, how to access the output? how to access the input? | 18:19 |
| olofk | GeneralStupid: Did you go for an 8-bit or 16-bit data port? | 18:46 |
| GeneralStupid | 16 bit | 19:14 |
| olofk | GeneralStupid: Ok, so "*(uint16_t *)0x94000000 = value" to write to register 0 in your core. If I understood things correctly, you only got one register, right? | 19:15 |
| dalias | olofk, better make that volatile uint16_t * | 20:00 |
| andrzejr | olofk, GeneralStupid, afair 16b access won't work without changes to wb_data_resize.v | 20:35 |
| andrzejr | I'll try to clean up my repository soon(ish). For now, the patch I'm using is at http://pastebin.com/2C4F1CQY | 20:38 |
| andrzejr | have we got any ready to use mii2rmii adapter? | 20:59 |
| GeneralStupid | olofk: yes... | 21:56 |
| GeneralStupid | olofk: that works with uint8_t | 21:57 |
| GeneralStupid | andrzejr: so i have to use 8 or 32? | 21:57 |
| --- Log closed Mon Oct 26 00:00:42 2015 | ||
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