IRC logs for #openrisc Sunday, 2015-10-25

--- Log opened Sun Oct 25 00:00:40 2015
-!- knz_ is now known as knz08:30
GeneralStupidhi anyone here?09:19
GeneralStupidIs there any vhdl example how to "connect" to the wishbone bus?09:20
olofkGeneralStupid: Great news that you got it working10:35
olofkThe size parameter in wb_intercon.conf just says how large address space to allocate for the core.10:36
olofkSo for example if you set offset=0x90000000 and size=32 for the UART, all addresses from 0x90000000 to 0x9000001f will be routed to the UART core10:37
GeneralStupidolofk: thats what i thought... So i may could control the lcd with 8 bits because it cannot display 256 characters but it is easier to use 10 bits (or 16...)10:38
olofkGeneralStupid: It sounds like you want to set the datawidth parameter then10:39
olofkI think only 8 and 32 bits are supported right now, but andrzejr has a patch for 16 bits10:40
GeneralStupidolofk: yes... of course...10:40
olofkjkent: Could you send over the error log? I haven't tried building it in a while so maybe something is broke10:40
GeneralStupidso size=2 means?10:40
olofkThe address space is two bytes, meaning that only address offset and offset+1 goes to the core10:41
olofkThis is used for the gpio core since it only has two one-byte registers10:41
GeneralStupidbut two bytes would be enogh for width 16, too or am i wrong?10:41
olofkIn the rtl code datawidth determines the width of the of the wb_dat_* ports, and size sets the width of the wb_adr port10:42
GeneralStupidbut i need some informations about the wb bus :)10:43
olofkWhat kind of info?10:43
GeneralStupidiam not really into verilog, at work we use vhdl :) So how do i connect a new component with that bus?!10:44
GeneralStupidWhat do i have to take care of?!10:45
olofkandrzejr: That's excellent news! I'm really keen on rewriting the wishbone BFM in cocotb or similar to make it easier to catch more corner cases for bursting10:45
GeneralStupidit would have been easier to just calculate something in hardware and send an interrupt if it is finished :)10:47
olofkGeneralStupid: There are plenty of examples of wishbone slaves written in VHDL. The i2c component for example has both an VHDL and verilog example10:47
olofkAnd you should probably read the wishbone spec as well10:48
olofkBut it's all quite simple for single accesses10:48
olofkwhen stb and cyc are both asserted, you look at adr to determine the requested address, we to see if it was a read or write request and wb_dat_i to get the data if it was a write10:49
olofkYou then assert ack to notify the master that you have taken care of the request, and for reads you return the data in wb_dat_o at the same time10:49
olofkNo need to worry about cti, bte, err, rty at this point10:49
GeneralStupidsounds okay :)10:50
olofkoh.. and if you use data ports that are wider than 8 bits you also need to check sel.10:50
GeneralStupidi thought databus would get to 15 downto 0 and thats it :)10:53
olofkIf you only do 16-bit accesses to the core, you don't need to handle sel10:54
GeneralStupidi just want to put 16 bits from my binary to my lcd stuff (for the first, simple example...)10:56
GeneralStupidi need to show that tomorrow, but the npc problem ...10:56
GeneralStupidthe next thing i want to try is some hardware calculations... i don't exactly know how to do this the best way (my experience: it depends on what i want to calculate)10:58
GeneralStupidbut that gets important if iam ready with that lcd ...10:59
GeneralStupidolofk: do you use an generator for some hdl stuff?11:00
olofkGeneralStupid: Yes, in some cases. The wishbone interconnect is generated11:07
olofkAnd I have made some slave generators in the past, but nothing for wishbone11:07
olofkAnd I'm looking at generating top-levels from IP-Xact descriptions11:08
jkentolofk: did you want to see more than the failing link?
olofkjkent: I was mostly hoping to see some error message that I recognized, but this isn't my strongest side, so I'm afraid I can't help you much with it :/11:16
GeneralStupidolofk: yeah, thats what you told a time ago... i hate that hdl is so redundant11:17
olofkjkent: Perhaps try --disable-sim. I don't think you need that11:17
jkentolofk: okay, i'll give that a go11:18
olofkA shot in the dark, but since the errors seems to come from libsim it's worth a shot11:18
jkenti'll show the waring with gas when i come to it11:18
jkentwell, error, because of -Werror11:18
olofkcool. These things always need to be adjusted for newer versions of glibc and gcc11:18
jkentolofk: --disable-sim did the trick, it linked11:28
jkentthank you!11:28
GeneralStupidi think i should do more verilog stuff... it looks much less to write11:29
GeneralStupidvhdl gives you the feeling that you program something :) verilog looks a bit strange to me (always?!)11:32
GeneralStupidolofk: why should wb_adr_i == 0 if i want to output data?!11:49
GeneralStupidolofk: input, sorry input :)11:49
GeneralStupidinput wb_adr_i == 1; output wb_adr_i == 0... I think i get it11:50
GeneralStupidwait a minute, it looks like it is not very complicated actually :)11:52
andrzejrolofk, not sure if better coverage would help here - in the simulation the output from the ddr2 controller behaves "as expected". I wonder if that has something to do with use of distributed RAM for caching in the xilinx code.12:10
andrzejrit looks like there is another bug in the code, because after fixing the first one I still get a bus error, just a bit later. When I simply disabled bursting support in my code (yes, I should have tried it a month ago) memory just works.12:13
andrzejrnot sure about that random freeze when booting linux. I've got it twice yesterday but wasn't able to reproduce it since.12:16
GeneralStupidolofk: i think i got it... i dont need size = 2, i need size = 117:21
GeneralStupidand then i just put my LCD module and map it ...17:21
GeneralStupidolofk: is there a way to simulate this?17:22
GeneralStupidcan anyone tell me how to access the output with newlib?18:09
_franck_GeneralStupid: use pointer, something like *(uint8_t *)0x92000000 = 0x1118:18
GeneralStupid_franck_: i have 0x94000000, how to access the output? how to access the input?18:19
olofkGeneralStupid: Did you go for an 8-bit or 16-bit data port?18:46
GeneralStupid16 bit19:14
olofkGeneralStupid: Ok, so "*(uint16_t *)0x94000000 = value" to write to register 0 in your core. If I understood things correctly, you only got one register, right?19:15
daliasolofk, better make that volatile uint16_t *20:00
andrzejrolofk, GeneralStupid, afair 16b access won't work without changes to wb_data_resize.v20:35
andrzejrI'll try to clean up my repository soon(ish). For now, the patch I'm using is at
andrzejrhave we got any ready to use mii2rmii adapter?20:59
GeneralStupidolofk: yes...21:56
GeneralStupidolofk: that works with uint8_t21:57
GeneralStupidandrzejr: so i have to use 8 or 32?21:57
--- Log closed Mon Oct 26 00:00:42 2015

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