| --- Log opened Sat Sep 26 00:00:00 2015 | ||
| stekern | allright, flights booked - I'll arrive 10 am on friday | 04:42 |
|---|---|---|
| blueCmd | stekern: I got nostalgic today troubleshooting something and I ended up writing this: http://blog.cmd.nu/2015/09/hardest-bug-i-ever-solved.html - do you remember that? :) | 16:57 |
| blueCmd | interesting with all the intel management engine talk going on (binary firmware with full DMA access etc) - might cause a boost in interest for open-source CPUs | 17:37 |
| olofk | stekern: Great! Will you be there the whole weekend then? | 18:02 |
| olofk | andrzejr: Great progress. So does this mean that the bug is in or1k_cache_init (is that in newlib btw?) or was it in your code? | 18:03 |
| olofk | andrzejr: And of course you should sneak away :) | 18:07 |
| andrzejr | olofk, I think that is either mor1kx or _or1k_cache_init. I think the problem is not with the cache itself (16B cache lines worked fine here) but with the detection of its size. | 18:36 |
| andrzejr | would be good to check if this affects other systems as well (just change the mor1kx parameters and see if newlib programs boot correctly). | 18:37 |
| andrzejr | now looking into booting linux, can I do that without eth, spi flash/sdcard and vga? | 18:39 |
| stekern | olofk: yup, plane goes back 19:00 sunday | 18:48 |
| stekern | blueCmd: I remember ;) | 20:41 |
| olofk | andrzejr: You only need a UART and memory to boot linux | 20:47 |
| olofk | Well, you don't really need a UART either, but it's really boring without one | 20:48 |
| olofk | andrzejr: What mor1kx settings would you like me to test? And does it have to be on hw, or is simulation good enough? | 20:49 |
| olofk | Very annoying that none of the JTAG adapters I have (Actel FlashPro4, Digilent HS3) are of any use with OpenOCD | 20:50 |
| olofk | I still haven't tried to use my de0 nano or ordb2a to route the JTAG signals through the chip and use them as JTAG adapters. Might work | 20:51 |
| andrzejr | olofk, try .OPTION_ICACHE_BLOCK_WIDTH (4) and .OPTION_DCACHE_BLOCK_WIDTH (4) in HW. Maybe also remove (make it default) IBUS_WB_TYPE, although this should not have an effect. | 21:57 |
| andrzejr | I'm currently using Digilent cable (the one built into the nexys4 board). Settings are in http://pastebin.com/RQrsABVk | 22:00 |
| --- Log closed Sun Sep 27 00:00:01 2015 | ||
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