IRC logs for #openrisc Thursday, 2015-09-24

--- Log opened Thu Sep 24 00:00:57 2015
andrzejr_franck_, do you know the sequence of TDI, TMS corresponding to the halt command? Couldn't get jtag_vpi to work so I need something with no dependencies on other software. I can see outputs of BSCANE2 toggling in HW when I issue the halt command but I do not get a response from adbg_top.07:32
-!- orsonmmz|away is now known as orsonmmz07:33
andrzejrmy openocd script:
olofkandrzejr: Would it help if I run a jtag_vpi test and provide you with some info?08:59
maxpalnolofk: Yes, away from ORPSOVv2 - although not entirely within Fusesoc either. That is my aim for this leg of work!09:03
maxpalnIn reality all the simulations I run are working fine - which makes me think it is a synthesis thing (that, and the fact that I discovered a synthesis problem during the initial testing with the inferred MAC - I worked around it by manually inserting a multiplier from our library)09:04
maxpalnwhich is another problem - the version of MOR1KX I use has this additional code - is there a way to force a local copy of a file into the build?09:05
maxpalnIf not, the standard checkout of MOR1KX will always have this problem until the synthesis problem is fixed!09:05
olofkmaxpaln: For FuseSoC you can create a new directory, check out mor1kx there, put mor1kx.core there with the provider section deleted and add that directory to fusesoc.conf09:08
olofkThen it will use your local version of mor1kx09:08
olofkoh... you want to do it for a single file09:08
olofkThat's not really supported by FuseSoC, but you can still use a local copy of mor1kx and manually keep that synced to upstream mor1kx with your changes09:09
maxpalnok, that works - a local copy is fine for now. Waiting for Synopsys to fix synthesis bugs is a notoriously patient business. An interim solution is definitely needed but longer term I'd hope to be using the standard checkout...09:14
maxpalnIf I get really keen I may also fix that remaining Wishbone BFM problem - the one where no byte-wide transactions are modelled. I remember losing around 3 days to diagnosing a bug that would have been found had I spent half a day implementing that!!!!!09:15
olofkmaxpaln: Yes, that would be great. andrzejr had a bug with byte/halfword accesses just a while ago, so having the BFM test that is clearly useful09:18
olofkAnd waiting for synopsys to fix things is not that fun. Last time I reported a bug, I think the product was released a long time before they got around to fix the bug09:20
olofkThe benefit of using open source tools09:20
olofkmaxpaln: Talking about open source tools, do you know if Lattice has said anything about the open source ice40 toolchain?09:21
maxpalnI don't remember hearing anything about open source tools for iCE40 - do you know something I don't? ;-)11:11
maxpalnand yes, the new BFM is a big improvement on the old one but the lack of byte/half word support is a glaring ommision - all HW will almost certainly exercise the interface in this way so testing it in sim is really essential. I#ll try and find time in the next few weeks or so.11:12
maxpalnActually, on the synthesis tools we are nearing the production release of our own internally developed synthesis enginer: LSE (no prizes for guessing what it stands for!)11:13
andrzejr_maxpaln, had a similar problem with cadence - the support came up with a set of optimisations that producing correct results11:14
maxpalnThis should make turnaround on bug fixes a lot quicker - its not quite as good at larger more complex designs at the moment though, so I am sticking with Synplify for now...11:14
maxpalnadrzejr: support from Cadence: impressive!11:14
andrzejr_afair the problem was in RTL rewrite option combined with power optimisation flags. the symptom was a broken multiplier when some of the signals were truncated11:17
andrzejr_as for byte/half-word access test - that would be great to have. I found several bugs already, some in my code, some in wb_interconn11:20
andrzejr_also, it would be good to have a behavioural (or even rtl) bus monitor reporting transactions and errors11:23
maxpalnandrzejr: do you mean in HW or in Simulation? There is a monitor for MOR1KX that is excellent for tracking instructions etc. But I guess what you want is to attach something to a particular bus interface and monitor it - not necessarily on the CPU, right?12:21
andrzejr_maxpaln, preferably both. in simulation for logging transactions and errors. in hw for counting them (debugging rare errors and performance issues)12:36
maxpalnActually this shouldn't be too tricky. its largely a variant on the BFM code - but instead of issuing transactions and comparing memory contents, it just checks the bus signals for compliance to the spec.12:55
maxpalnActually now I think about it - this could be a sizeable piece of work depending on how much of the spec is implemented.12:55
maxpalnBut a relatively common subset of cycle types would straight forward enough - it could be made synthesizable too. The challenge is how to get the information out of the HW after a fatal error....12:56
andrzejr_in my sdram ctrl I'm planning to add a couple of counters (transactions and bytes) that can be read back by sw. but that's purely for performance monitoring and it doesn't distinguish between bus masters.13:54
maxpalnSO, I think my strategy is going to be to get my current project running inside fusesoc - simulation, HW build and all. I can then update all the relevant parts that have been updated since I last pulled them down.14:05
maxpalnI have a fusesoc checkout from around 9 months ago - I guess I should update that first. Then go about creating a new system etc.14:06
maxpalnwithin fusesoc how do you control what simulations are run? I'd like to run a set of CPU regressions on the MOR1KX - is that something that can be done within fusesoc?14:26
maxpalnI suppose more accurately, I want to get to the point where I can run some system level simulations that exercise and test the CPU within my ORPSOC build. I am guessing this is possible but being a newbie it isn't clear how to get to that point. I'll keep digging....14:28
maxpalnhmmm, I decided to try 'fusesoc sim mor1kx-generic' - I figured that might get me closer to my target. I get an odd error though:14:33
maxpalnI wonder if I have an out of date version of something.. I thought I had cleaned and update it all....14:36
maxpalnI think that was it - I had an old set of files at /root/.cache/fusesoc - not sure what process checks these but I guess something assumed they were up to date. I deleted the lot and retried my 'fusesoc sim mor1kx-generic' command - it pulled down a new set and got further before erroring with a pretty opaque message about failing to build simulation model.14:40
maxpalnit seems I am missing libelf!14:42
maxpalneven more curious - elfutils-libelf is installed but gelf.h is proving elusive to the compiler.... why is it always my linux knowledge that befuddles me....14:58
andrzejr_a missing -dev package?15:01
maxpalnI was just thinking along those lines - libelf is installed but not libelf-dev15:01
maxpalnwhoop - back in business!15:03
olofkmaxpaln: Great to hear it works15:03
olofkThe cache mechanism in FuseSoC is one of those thing I've intended to improve for several years now15:03
olofkManually clearing out the cache is the best solution for now to get around strange errors15:04
maxpalnor at least I think so - it looks like the sim is running (top shows vvp running at ~100%) but the last thing printed to the screen is 'No ELF file specified'15:04
maxpalnguess i'll wait to see if it all runs ok15:04
maxpalncan the sim be made more verbose?15:04
olofkmaxpaln: Try fusesoc sim mor1kx-generic --help15:05
maxpalnah, the help is context sensitive - nice!15:05
olofkYep. One of those less advertised features of fusesoc :)15:06
olofkSo you probably want to load an elf file with --elf-load=/path/to/elf at least15:06
olofkWhat sim are you using btw?15:07
maxpalnI guess icarus - I haven't specified anything else15:08
maxpalnI wanted to try something that should definitely work - then build up15:09
olofkJust curious if you had seen the --sim=<simulator> parameter15:09
maxpalnI don't think I did - at least not in the helps I have seen so far.15:10
maxpalnI see modelsim is supported now - I have riviera which accepts modelsim commands. I will try that next but I suspect some of the command options will be different.15:10
maxpalnIs it a big deal to add support for a new simulator?15:10
olofkIt's context sensitive, so you need to put the --help after the sim command, but before the system :)15:10
olofkShouldn't be a big thing. andrzejr added support for Xilinx xsim and Isim that I haven't merged yet15:11
maxpalnI don't know python too well but it would be cool to have support built in for riviera (or active-hdl for that matter seeing as we ship a copy with Diamond.15:11
olofkI'd love to have support for more sims and Lattice tools15:11
maxpalnwhereabouts should I start looking to add support for the new sim? Just give me a starting point and I'm sure I'll figure it out...15:12
olofkI've actually added support for icecube2, but haven't pushed it yet, since I haven't got any HW to test it with15:12
maxpalnBTW, how long should 'fusesoc sim mor1kx-generic' take? I have trace_enable and trace_to_screen enabled and am at '32500000.00 ns' so far...15:12
maxpalnah, you should have said - which device? I am pretty certain we have some of those low cost boards in our office.15:13
maxpalnI guess you want something with a larger device - the biggest is an 8K LUT I think -15:13
maxpalnon this board15:13
maxpalnthere's not much on the board - its designed to provide access to all the IO via headers.15:14
olofkmaxpaln: I just did a small test design to test the toolchain. Think I actually managed to synth a minimal mor1kx for one of the 8k devices, but it was some time ago, so I might misremember15:14
olofkmaxpaln: Simulation length depends on the elf you run I guess15:15
maxpalnI didn't specify an ELF - in fact this was one of the first messages 'No ELF Specified' although its run off the top of the screen.15:16
maxpalnIs there a default ELF or some default tests?15:16
olofkNo default ELF15:16
olofkBut we have a repo with som standard tests up now15:16
olofk(I think)15:16
maxpalnhmm, ok let me look15:17
olofkHmm.. If I only could remember how to compile the damn test suite... stekern? :)15:18
maxpalnok - so this is pretty different to last time I looked. What's the process for generating an ELF for fusesoc..15:18
maxpaln(ah, ok - so we need stekern's help) :-)15:18
olofkmaxpaln: Nothing special. Just gcc15:18
olofkI can provide you with a few elfs that you can test15:19
maxpalnwell, that would be good - but I'd really like to try running a full mor1kx regression suite. So, I guess I'll have a look in the Makefile to see if there are clues...15:19
olofkI generally run or1k-basic for quick tests15:20
olofkUnfortunately it's not passing all tests in the suite since some of them depend on some peripheral mapped to a certain address, or that the memory should be of a certain size15:21
olofkIt's more or less the old tests from orpsov2 and mor1kx_dev_env with some fixes applied15:21
maxpalncool, this is looking a bit more familiar - the names at least...15:22
olofkIf you want to run all the elf files with a script, I recommend that you pass --keep to fusesoc. That avoids rebuilding the simulation model prior to every run15:22
olofkHungry baby. Must feed15:23
maxpaln:-) thanks - as always, much appreciated15:23
maxpalnif you'd like an iCE40 board BTW let me know - I'll have one shipped if we have a spare in our office.15:24
olofkOh...tempting. I've never said no to hardware :)15:29
maxpalnhmmm curious - I am getting errors about undefined functions that should be defined in libelf as far as I can tell:15:33
maxpalnelf-loader.c:39: warning: implicit declaration of function ‘elf_getphdrnum’15:33
maxpalnthis causes:15:33
maxpalnvvp: symbol lookup error: ./elf-loader.vpi: undefined symbol: elf_getphdrnum15:34
olofkmaxpaln: What's your libelf version? We had problems with 0.147 (or something like that)15:34
maxpalnhmmm, quite old if that was the version you had problems with...15:34
maxpalnelfutils-libelf-devel.x86_64               0.137-3.el5                 installed15:34
olofkJesus christ. Are you running on Eniac or something?15:35
maxpalnit is the one part of my IT setup that is pretty old. I have a pretty old linux VM. I have been meaning to setup a new one but as far as I can tell it will require the company to splash some cash, a tricky ask at the moment...15:36
olofkThere's probably some way to get compile and use a newer version of that lib, but it's not part of my skillset15:37
maxpalnyeah, that is what I am thinking...15:37
maxpalnhmmm, yum isn't offering me anything newer - I wonder how painful it will actually be to manually install these. Diving in...15:39
maxpalnhmmm, it seems 0.137 is latest version officially listed for CentOS5...15:41
olofkPerhaps you just need to build the thing and set ld_library_path. Or find a new rpm15:41
maxpalnI'm straying from the path now...15:41
olofkThe elf-loader is for parsing an elf file and preloading the RAM. There are other slightly more complicated ways to run programs15:46
maxpalnwell, I am starting to think I should consider getting a newer Linux distribution on my VM. I see VirtualBox is a free tool instead of the purchased VM-Ware that our company issues. Does anyone have any experience?15:48
maxpalnits a ballache though - it will mean taking at least a day out to reinstall the tool chain and all the other dependancies....15:49
maxpalnalthough I would be shiny and new tough #tempting15:49
olofkI use VirtualBox all the time. Works just fine for these kind of things. USB passthrough is usually good enough to program boards from inside the VM as well15:49
maxpalnok - well it seems straight forward enough to get installed. Maybe I'll try this tomorrow as a background activity...15:50
olofkAnd the or1k gcc toolchain is available precompiled nowadays, so you hopefully don't have to do that at least15:50
maxpalnah, that would be simpler - what about the LInux tool chain, IIRC there were two separate tool chains (or something like that)15:53
olofkwallento: Do you know ^ ?15:53
olofkActually, to build linux itself, you use the newlib toolchain (which I know is available)15:55
olofkFor building programs to run under linux you can use the uclibc or musl toolchains. I think the last one is preferred, but I don't know if they are available precompiled. Perhaps it's just as easy as taking a copy of mine15:55
maxpalnI don't mind recompiling stuff - if I have a new distribution of Linux it should be straight forward enough as the tools to get dependencies etc. will be very useable. Its more a case of knowing what to install. I wrote some notes when i did it last time - I'm just trying to find them...15:57
maxpalnah, here we go:15:59
maxpalnseems pretty up to date(ish)15:59
olofkYeah, I put some effort into updating that a few months ago15:59
maxpalnit should get me going int eh right direction - I think I'll track all my steps and keep a guide. Seeing as i am installing Linux from scratch this should be a pretty good how-to guide.16:00
olofkHey, that's cheating! Everyone is supposed to keep the instructions in their heads. No guides are allowed16:06
-!- olofk_ is now known as olofk16:24
_franck__andrzejr: with this,filedetails?repname=adv_debug_sys&path=%2Fadv_debug_sys%2Ftrunk%2FHardware%2Fadv_dbg_if%2Fdoc%2FAdvancedDebugInterface.pdf16:46
_franck__and openocd source code you should find what you want16:46
stekernolofk: "stekern?" doesn't highlight in irssi18:32
stekernbut it should just be to run 'make' in the native directory (if you didn't figure it out already)18:33
olofkstekern: I think the problem was that everything was already compiled18:44
olofkstekern? sucks!18:44
stekernthat highlighted...18:46
olofkok, so now I've booked hotel too19:03
stekernwhich one?19:03
olofkNash airport hotel19:04
olofkWas going to book at Ibis since a lot of other people seem to stay there, but I think they are out of rooms for thursday->friday19:04
olofkAccording to "shopping, lakes and museums" are three good reasons to visit Geneva. I somewhat suspect that I will see none of those19:05
stekernI still need to nail down which days I can be there19:08
andrzejrhas anyone had problem displaying waveforms in ascii format in gtkwave? The waveform contents is a correct ascii string but when I switch on the ascii format I get rubbish. Also checked with bit reverse and right justify.20:18
-!- orsonmmz is now known as orsonmmz|away20:47
andrzejr_franck_, good news - I can simulate orpsoc+jtag+openocd+gdb, had to add a jtag tap simulation model (JTAG_SIME2 - for some reason no one seemed to use e.g. JTAG_SIM_SPARTAN6 before).21:22
andrzejrminor glitches in the tooling, for example "info spr sys" in gdb results in "invalid command name "readspr""21:23
andrzejrbad news: other than adding the simulation model, no changes were required. So I still don't know what is happening in HW21:24
andrzejrBTW, in the simulation I can use BSCANE2's SEL and RESET outputs. But the simulation fails if I route DRCK to adbg_top instead of TCK.21:26
andrzejrOne difference is that the simulation model uses IDCODE=0x03631093 and the actual chip 0x13631093 (version 1 instead of 0).21:58
andrzejrwith slightly different connections (simulation still works) in HW I get:22:17
andrzejrWarn : CRC ERROR! Computed 0xdebb20e3, read CRC 0x0000000022:17
andrzejrError: Burst read failed22:17
andrzejrnot sure if that's a step forward or back22:17
andrzejryay, it works! there may be something wrong with synthesis, though. I'm pretty sure I tried this combination of connections between the tap and the adbg_top before.23:12
--- Log closed Fri Sep 25 00:00:58 2015

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