| --- Log opened Wed Sep 23 00:00:17 2015 | ||
| --- Day changed Wed Sep 23 2015 | ||
| _franck__ | andrzejr: what signal did you hooked up here: https://github.com/openrisc/orpsoc-cores/blob/master/systems/atlys/rtl/verilog/orpsoc_top.v#L408 ? | 07:28 |
|---|---|---|
| -!- orsonmmz|away is now known as orsonmmz | 07:28 | |
| andrzejr | hi _franck_, BSCANE2.SEL | 07:29 |
| _franck__ | BSCAN code in openocd does not have any instruction to enable the debug core (something like this in altera VJTAG: https://github.com/openrisc/orpsoc-cores/blob/master/cores/altera_virtual_jtag/altera_virtual_jtag.v#L107) | 07:30 |
| andrzejr | btw, I've just found I was using a different version than the default one in orpsoc-cores, afair from git master branch | 07:30 |
| andrzejr | I see, thank you, will try that | 07:31 |
| _franck__ | a different version of what ? | 07:31 |
| andrzejr | of adv_debug_sys | 07:31 |
| _franck__ | may be you should try to force debug_select_i to '1' | 07:31 |
| _franck__ | or at least output this signal to a led to see its level | 07:32 |
| andrzejr | is it possible to debug the jtag tap in simulation? I can access BSCANE2 via glbl instance but do we have any simulation model for "jtag master"? | 07:32 |
| andrzejr | will do that, I have to leave for work soon | 07:32 |
| _franck__ | yes we can connect openocd to a simulated soc, just have to remember how :) | 07:33 |
| _franck__ | andrzejr: you need to use this interface http://repo.or.cz/openocd.git/blob/HEAD:/tcl/interface/jtag_vpi.cfg | 07:36 |
| andrzejr | If we can define a sequence of JTAG commands to send it should be easy to write a simple bfm model. | 07:36 |
| andrzejr | I've got it already (from atlys) but haven't tried if it still works | 07:37 |
| olofk | andrzejr: I guess the problem would be that you might need ISIM or XSIM with the BSCAN model, and none of those support vpi | 10:19 |
| olofk | GeneralStupid: Don't worry. You're not forgotten :) | 10:23 |
| maxpaln | howdy all, after a few months of absence - I am back on the ORPSOC port to our eval board :-) | 15:14 |
| poke53281 | wb | 15:15 |
| maxpaln | I have a few housekeeping things to do first though - I have pulled in a new version of the MOR1KX for ages and my simulation test suite also hasn't been updated since I was still working on the OR1200!!!! | 15:15 |
| maxpaln | poke53281: thx | 15:16 |
| maxpaln | I remembered that in my implementation I had switched out the RTL multiplier for an instantiation of our hard coded multiplier block. I switched 'FEATURE_MULTIPLIER' to PIPELINED and rebuilt the design but it doesn't work. I'm just trying THREESTAGE - but should these all work when booting Linux? | 15:46 |
| maxpaln | I suspect this is a synthesis issue (the same one that caused me to instantiate one of our multipliers directly. But I thought it worth investigating. | 15:51 |
| andrzejr | maxpaln, what board? | 17:45 |
| andrzejr | olofk, fortunately BSCANE2 is not encrypted. | 17:48 |
| olofk | andrzejr: Ah, that helps | 18:45 |
| olofk | maxpaln: HAven't really played with the different multiplier options. Have you tried them in simulations? | 18:46 |
| olofk | And I hope for god's sake that you have switched away from ORPSoCv2 to FuseSoC now ;) | 18:46 |
| -!- orsonmmz is now known as orsonmmz|away | 19:37 | |
| --- Log closed Thu Sep 24 00:00:57 2015 | ||
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