IRC logs for #openrisc Tuesday, 2015-09-22

--- Log opened Tue Sep 22 00:00:54 2015
--- Log closed Tue Sep 22 00:24:26 2015
--- Log opened Tue Sep 22 00:24:39 2015
-!- Irssi: #openrisc: Total of 46 nicks [0 ops, 0 halfops, 0 voices, 46 normal]00:24
-!- Irssi: Join to #openrisc was synced in 8 secs00:24
andrzejroh my, found it. don't ask01:12
olofkandrzejr: haha. That last sentence made me pretty curious :)08:51
-!- orsonmmz is now known as orsonmmz|away16:56
andrzejrolofk, nothing special, an error in a bus adapter. But it was difficult to reproduce and resulted in flooding SDRAM with "sr requests". So the symptom was that occasionally the whole system was slowing down 10x.18:38
olofkGeneralStupid: Have you had any time to work on the de2 port for FuseSoC?20:10
GeneralStupidolofk: sadly i have to schedule this at the end of october20:11
GeneralStupidolofk: :/ Iam working in automotive (not VW ;-)) *and* i have exams every two weeks20:11
olofkSounds like you have lots of spare time :)20:13
olofkOh well. Let me know if you need any help once you get around to do some stuff with the port, and good luck with the exams20:13
GeneralStupidolofk: i need holidays, i really do :)20:13
olofkGeneralStupid: I know the feeling :)20:13
olofkRight now I need to sleep. Good night20:14
GeneralStupidolofk: good night. BUT nice to know that you dont forget me ;)20:15
andrzejrI can use openocd to read fpga id etc, so I assume the connection to the chip is working. However, the halt command times out. I guess this is because a problem between the tap (BSCANE2 and the debug interface).21:52
andrzejranything I can do to debug this issue a bit further? (I'm new to openocd and have never seen/used it when properly configured)21:53
andrzejr_franck_ ^ (sorry for poking, looks like you are the most familiar with this topic)21:58
--- Log closed Wed Sep 23 00:00:17 2015

Generated by 2.15.2 by Marius Gedminas - find it at!