IRC logs for #openrisc Thursday, 2015-08-13

--- Log opened Thu Aug 13 00:00:57 2015
andrzejrSo, I have enabled the cache SR.ICE=1, ICCR.EW=0xff so now the cache is actually being accessed. But it still produces X's on cpu_dat_o so the cpu hangs on "unknown opcode 0xxx". Anything else to set?00:48
stekernandrzejr: what is the code you are trying to run?03:09
-!- Netsplit *.net <-> *.split quits: antgreen, Shentino07:41
-!- Netsplit over, joins: antgreen, Shentino07:42
andrzejrstekern, I'm debugging the hardware, rom and ddr2 i/f, so I wrote a simple testcase in assembler to read/write some RAM locations.07:55
andrzejrto summarize: cpu issues bus bursts but initially the (instruction) cache is off so bursts make no difference. I have enabled the cache as shown above but then the cpu hangs (cache returns X's)08:02
andrzejrThis code ( hangs 1 instruction after setting SR.ICE=1 - "Unknown opcode 0xxx" (*.mor1kx_icache.cpu_dat_o is stuck on 32'bx)08:16
latifolofk: For orpsoc-v2 , I did many things successfully, adding IP modules, booting spi flash ... etc. But I did NOT try to add something in bootrom.v.. My applications (like LED blinker) were made using C language, not by adding something to bootrom.v ...For V3 I could not manage even boot it from spi. So, I could not try something else..08:32
latifolofk: There were a few guy here on this channel and They said that they can boot v3 from spi. I wanted them to send me their bootrom.S bootrom.v and rom.v files. After they sent, I realised that their codes are different from each other and my bootrom.v code (from v2). Then I tried their bootrom codes on my computer but the result was the same again. It ddin NOT work.. I dont know how these guys boot v3 from spi, or are they using an08:36
stekernandrzejr: do you invalidate the caches before turning them on?09:03
olofklatif: I know that you're having trouble booting from SPI, so I think the best way forward is to try to figure out exactly what the problem is. I can see several potential issues so we should narrow it down a bit first10:48
olofkPotential issues could be:10:48
olofk1) The boot ROM is never executed10:48
olofk2) The code fails to read from SPI Flash10:49
olofk3) The code reads at the wrong location from SPI Flash10:49
olofk4) The image is broken in some way10:50
olofk5) The image is not copied properly to RAM10:50
olofk6) Everything is copied ok, but the image in RAM is never executed10:50
olofkIf you have an oscilloscope it would be great if you could measure the SPI lines to the Flash. That would let us know if it tries to read anything at all10:51
olofkMy sugggestion of putting a LED blinker in boot ROM was to see if it was executed at all (Issue 1)10:52
olofkIf you have a debugger, you could read out the RAM to see if anything was written there10:53
latifolofk: While I was working on orpsoc-v2, I used an oscilloscope to measure the spi lines on Atlys board. But I did not do it for v3. I will try to do it today. But first, I will not add something to bootrom.. Then I will make the measurments to see wheter the rom is executed.11:31
olofkSounds like a plan. Let me know what happens11:32
latifBut there is problem..11:32
olofkI started work on improving the booting situation a few months ago, but I have only had time to properly finish it for de0_nano11:33
latifwhich bootrom.v code should I use??11:33
latifthe bootrom.v from orpsoc-v2??11:33
olofkI honestly don't know11:34
latifor the codes which are sent me by some guys from this channel. :) they are all different..11:34
olofkI guess that since some people have managed to boot from the one in the Atlys port in orpsoc-cores, I guess that should be your first choice11:35
latifok. then. firstly, I will use the bootrom.v code from v2.11:35
latifthen I will try the others..11:36
latifI will share my measures from here if I can understand something..11:38
andrzejrstekern, that was the issue (or at least a part of it). I did't expect invalidating cache is required but since tags are kept in ram that makes sense19:15
andrzejrnot sure why, but if I enable cache ways (ICCR.EW) before enabling the cache (SR.ICE) I get some sort of a lock-up. Even when the cache was previously invalidated.19:18
olofkwallento: Regarding disabling gdb, IIRC we haven't upstreamed GDB so we're still using the old or1k-src repo to build that21:05
wallentoah, okay21:05
wallentoI was maybe just confusing it21:05
wallentothanks olof21:06
olofkwallento: This of course makes me a little confused about what the binutils-gdb repo contains :)21:07
wallentolike newlib-cygwin21:07
wallentohow about renaming to mor1kx-doom? ;)21:07
wallentothanks for clarifying, I will adapt the automated builds21:12
olofkwallento: Ahh.. that's a fork of upstream binutils-gdb?21:17
wallentowill use or1k-src solely for gdb21:17
wallentoupstreaming has the same problems as gcc?21:18
olofkI don't think so actually. Just that no one has gotten around to do it21:18
wallentoah, okay21:20
--- Log closed Fri Aug 14 00:00:58 2015

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