IRC logs for #openrisc Friday, 2015-08-14

--- Log opened Fri Aug 14 00:00:58 2015
andrzejrDoes Mor1kx support bursting on data bus? B3_REGISTERED_FEEDBACK issues only burst termination transactions, CLASSIC and READ_B3_BURSTING seem to be equivalent (classic WB access).00:10
andrzejrIdeally, Mor1kx should be able to send bursts of 4x32b words to quickly fill/read a single DDR2 burst (Wrap-4 mode).00:13
andrzejrREAD_B3_BURSTING works fine on the instruction bus, especially with OPTION_ICACHE_BLOCK_WIDTH=400:21
stekernandrzejr: yes it does bursting on databus with B3_REGISTERED_FEEDBACK03:19
stekernonly for reads though03:19
stekernyou should only use B3_REGISTERED_FEEDBACK together with cappuccino03:20
andrzejrstekern, I forgot to enable data cache ;-) Now I can see that with B3_REGISTERED_FEEDBACK I do get read data bursts07:57
andrzejrFor write access I get a bunch of burst termination transactions (cti=111) in the same bus cycle (cyc).08:00
andrzejrMy DDR2 interface does not try to merge WB transactions (in fact it may even split them if a WB burst does not match a DDR2 burst), so each written word will end up in a separate DDR2 transaction.08:07
andrzejrunless there is some extra optimization (transaction merging) in the Xilinx code08:07
olofkandrzejr: Memory interfaces is an area that definitely could need some improvement. I was working on several things earlier this year but never got time to finish anything11:04
olofkAllowing wider buses in mor1kx for example would be great so that you can transfer DQ_WIDTH*4 bits in one cycle to maximize throughput11:06
olofkAs part of that work I created a memory controller with a wide bus and a wishbone upsizer so that it could be used by 32-bit masters11:07
olofkBut what you're describing seems like another improvement to be implemented. It would make sense since I guess we're already writing a whole cache block11:09
olofkIIRC, my upsizer tried to merge transactions as well, so that could help here11:10
olofkIt's not bug free yet however.11:11
olofkApparently I have already pushed it to github despite it's not working properly yet, so here's the code if you're interested
andrzejrhi olofk, I agree. Ideally we would have two buses, (1) a simple point-point transport between cache, memory, a bidirectional bridge to a peripheral WB bus and perhaps some high speed IOs (DMA, VGA?) and (2) a low bandwidth peripheral WB bus for everything else.16:55
andrzejrI've been looking at mork1kx and found some limitations. It boots with caches off, so at least initially such transport would be inefficient (e.g. 32b out of 128b/256b would be used). Also, at least atm it does not write data in bursts, I guess this is a limitation of the cache controller, not the bus interface.17:02
andrzejrso, for now I am using the usual WB system bus and trying to pack DDR2 bursts and cache lines into WB bursts but WB protocol makes it fairly complicated. At least if I want to support many transaction types.17:05
mor1kx[mor1kx] bandvig pushed 1 new commit to marocchino_devel:
mor1kxmor1kx/marocchino_devel 149465b Andrey Bacherov: Some improvement for fetch. As a result, we don't need "fetch_valid" flag to control pipeline. Plus options FEATURE_DSX, FEATURE_MSYNC, FEATURE_ATOMIC, FEATURE_DATACACHE and FEATURE_DMMU have been made not configurable (always ENABLED).18:44
_franck_andrzejr: data cache does not write in burst because it is write through so data are written to memory at the same time they are written to cache18:47
_franck_we would need a write back cache to use write bursts18:48
andrzejr_franck_, I thought mor1kx already has a write back cache. But looking at the bus it indeed writes data it is currently processing.23:36
--- Log closed Sat Aug 15 00:00:00 2015

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