| --- Log opened Fri May 01 00:00:30 2015 | ||
| GeneralStupid | okay :) I need some more informations :) is there a documentation for newlib / openrisc what C libraries i can use? | 07:04 |
|---|---|---|
| olofk | GeneralStupid: Not really. We have found some code that requires patches to be built on OpenRISC, but I think most of the stuff works | 07:05 |
| olofk | At least under Linux | 07:05 |
| olofk | For bare-metal wih newlib I'm less sure | 07:06 |
| olofk | GeneralStupid: Have you come across a particular lib that doesn't seem to work? | 07:07 |
| GeneralStupid | olofk: no im still at the beginning, i only compiled some printf stuff | 07:08 |
| GeneralStupid | i would like to know if there is any nice way to access leds or switches | 07:09 |
| olofk | gpio | 07:09 |
| GeneralStupid | i have some of them on my board (DE2) | 07:09 |
| olofk | We generally map gpio to address 0x91000000, so if you do the same on your board you should be able to reuse one of our fancy led blinkers | 07:11 |
| GeneralStupid | i have for example led_r_pad_o connected in the pin plannet | 07:11 |
| GeneralStupid | planner | 07:11 |
| GeneralStupid | iam more a vhdl guy but it looks like their not connected in the top level | 07:14 |
| olofk | GeneralStupid: Are you using FuseSoC? | 07:15 |
| GeneralStupid | olofk: yes | 07:15 |
| olofk | Let me know if you want me to take a look at the code. A de2 port would be a welcome addition | 07:16 |
| GeneralStupid | olofk: at the moment i just changed the pin planner, technically the DE1 and DE2 are nearly the same... | 07:16 |
| GeneralStupid | should i paste the toplevel for you? I dont understand why there are some led outputs defined but never used | 07:18 |
| GeneralStupid | i just tell you how i understand the openrisc architecture: I have one WB Master and some WB Slaves. One of the slaves is GPIO, a 8 bit GPIO interface. So should i instantiate a second GPIO, and connect it to the bus, to use my LED's? | 07:21 |
| olofk | What is the first GPIO instance connected to? | 07:23 |
| GeneralStupid | there are connected to gpio_io and i pin planned them to a pin header | 07:25 |
| olofk | You could use those for the LEDs | 07:26 |
| GeneralStupid | ok, but just for example, what if i wanted to use more? i have 64 GPIO pins 25 LEDs, 4 buttons, seven segment display, LCD and 18 Switches :)( | 07:28 |
| olofk | Ah ok. Yes. Use separate instances for the other ones. Each gpio instance handles 8 bits | 07:29 |
| olofk | of course, no one is stopping you from creating a 32-bit version of the core | 07:30 |
| GeneralStupid | thats the normal way? because technically i need GPI and GPO and GPIO ? :-D | 07:30 |
| GeneralStupid | so in opensoc speach GPIO is one core? | 07:30 |
| olofk | :) | 07:31 |
| olofk | Yes to all questions | 07:31 |
| olofk | I usually remove the tristate buffers from the top-level to get GPI or GPO functionality | 07:32 |
| olofk | As we usually use them to interface LEDs or switches, we only need one direction as you have noticed | 07:33 |
| GeneralStupid | nice. whats cleaner? i once learned that 4 8 bit things are more flexible then 1 32 bit | 07:33 |
| GeneralStupid | ok i see it. Thats pretty clever designed, so you really can use the GPIO core for everything. | 07:34 |
| GeneralStupid | do i waste wishbone capacity by only using 8 bits? | 07:34 |
| olofk | Here's an example of a GPIO core connected to four switches and only used as input https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/rtl/verilog/orpsoc_top.v#L929 | 07:35 |
| GeneralStupid | the wishbone address keeps the same? | 07:36 |
| GeneralStupid | wb_m2s_gpio1_adr[0] | 07:36 |
| GeneralStupid | ok, i thought that would be more complex | 07:37 |
| GeneralStupid | iam new to verilog. i think {4'h, gpio_i} means 0000 0000 (last four '0' = button state) | 07:40 |
| olofk | GeneralStupid: It's concatenation (like "0000" & gpio_i in vhdl) | 07:42 |
| olofk | There's only two registers in the gpio core so we only need a single address bit to select between them | 07:43 |
| GeneralStupid | ah :) ok. Good. is it just limited to my FPGA how many slaves i connect? | 07:44 |
| olofk | Address decoding logic will increase for more slaves, but I don't think that's a real problem | 07:46 |
| GeneralStupid | how does addressing work? | 07:46 |
| GeneralStupid | i got it ok | 07:47 |
| GeneralStupid | in wb_intercon.vh? | 07:53 |
| GeneralStupid | that thing is generated by wb_intercon_gen :/ | 08:00 |
| olofk | Yes. It's really boring to write these things by hand :) | 08:02 |
| olofk | You have the input file to wb_intercon_gen located in data/wb_intercon.conf | 08:02 |
| olofk | gtg | 08:04 |
| GeneralStupid | thanks | 08:04 |
| GeneralStupid | AHH that board got 70 GPIO pins | 11:17 |
| GeneralStupid | I will put my de2 "design" into my github repo. I think you could then merge it easily?! | 11:18 |
| GeneralStupid | What is a good offset value. i mean, i dont really need such a big offset between the GPIOs right? (6bits) | 11:39 |
| olofk | Are you really really really sure you need to expose all of them as addressable GPIO? :) | 11:56 |
| olofk | gtg | 11:57 |
| GeneralStupid | olofk: i think it makes sense if i make a template? | 12:25 |
| GeneralStupid | Oh, i see :) I dont need to because it could make sense if you want to use GPIO from an component?! | 12:26 |
| latif | olofk: when applied the changes you said to me, xilinix successfully generated bit file. Thank you so much for all.. | 16:48 |
| --- Log closed Sat May 02 00:00:31 2015 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!