| --- Log opened Sat May 02 00:00:31 2015 | ||
| GeneralStupid | olofk: the de2 port is working out of the box like it is right now. | 10:00 |
|---|---|---|
| GeneralStupid | olofk: not spectacular but... maybe it helps some other people who just need an easy and free to use CPU | 10:07 |
| GeneralStupid | olofk: https://github.com/generalstupid/de2 | 10:07 |
| olofk | GeneralStupid: Great news. There have been a number of people looking for a de2 port actually | 11:11 |
| olofk | Oh, just fucking great. Altera has removed support for Cyclone III in Quartus 14.0 so I can't build it | 11:15 |
| olofk | ...or did I just skip installing the Cyclone III files | 11:15 |
| olofk | Looks like its both :( | 11:19 |
| olofk | Ah, it's even cyclone II | 11:31 |
| olofk | So 13.0 SP1 is the last supported version | 11:32 |
| bandvig | Hello, all. I'm deep diving into cappuccino source code, particularly into LSU. I have got several preliminary observations. | 12:02 |
| bandvig | (1) LSU isn't pipelined. (2) Data cache is VIPT (Virtually Indexed and Physically Tagged). I suppose the same to instruction cache. Am I right? | 12:02 |
| stekern | yes | 12:02 |
| bandvig | stekern: Is there difference (from a software support algorithms) between VIPT and PIPT caches? | 12:05 |
| stekern | it can be, but as long as you don't go cache size/way > pagesize you don't have to worry about it | 12:07 |
| bandvig | I suppose, the actual OpenRISC/Linux platform meet the condition :) | 12:09 |
| GeneralStupid | olofk: no | 12:23 |
| GeneralStupid | olofk: and yes, iam using 13.0sp1 too | 12:23 |
| stekern | at least you can still download 13.0sp1 | 12:26 |
| GeneralStupid | yes but its stupid. I have to install both parallel. | 12:27 |
| stekern | mmm | 12:27 |
| stekern | I even have an old 12.1sp1 laying around | 12:27 |
| GeneralStupid | Okay, iam normally no baremetal guy... how can i access to the GPIO stuff in C? | 12:27 |
| GeneralStupid | do i have to address them manually? | 12:28 |
| stekern | can't remember if there was something that only worked with that version, so I don't dare to remove it | 12:28 |
| GeneralStupid | stekern: and that is a bad thing i think. The newer version should also keep support for older boards. | 12:28 |
| GeneralStupid | we have a lot of these boards lying around and we are a bit screwed now... | 12:29 |
| stekern | GeneralStupid: port direction is at 0x91000000 and logic level at 0x91000001 | 12:29 |
| stekern | and 1 means out, and 0 means in | 12:30 |
| stekern | so to set all 8 ports to out: *((volatile uint8_t *)0x91000000) = 0xff; | 12:31 |
| stekern | and to set all outputs to 1: *((volatile uint8_t *)0x91000001) = 0xff; | 12:31 |
| bandvig | stekern: Am I right about that actual typical cache configuration doesn't require any special support VIPT cache in Linux? | 12:37 |
| stekern | yes, but you can easily calculate it | 12:38 |
| stekern | pagesize is 8kb | 12:38 |
| stekern | and sets*blocks shouldn't exceed that | 12:40 |
| stekern | i.e., typical settings are OPTION_DCACHE_BLOCK_WIDTH = 5 and OPTION_DCACHE_SET_WIDTH = 8 | 12:44 |
| bandvig | thanks, I've uderstood. Typically the cache way is exactly 8kb (13 bits address width). | 12:47 |
| GeneralStupid | stekern: Thank you | 13:14 |
| GeneralStupid | stekern: so i can do 0b01010101 to put every second LED to on? for example. And 0xff is out, 0x00 is in? | 13:22 |
| GeneralStupid | so iam able to configure every single port / bit different | 13:22 |
| stekern | right | 13:22 |
| latif | hi all | 15:08 |
| latif | olofk: I need your help again :) | 15:08 |
| latif | olofk: I am trying to do this tutorial... http://www.rte.se/blog/blogg-modesty-corex/loading-and-executing-program/2.7 .. I think I am doing every thing correctly but at the end it is not working :( | 15:10 |
| latif | olofk:What I am doing is that I am trying to write the orpsoc.bit and a ledtest program to the SPI flash and then so whenever I power on the ATLYS it starts to boot it from SPI flash and light up the LEDs.. | 15:13 |
| latif | olofk: ...It is the same as in the tutorial... I am following the same steps and makind generated all needed files and programing SPI flash with .mcs file successfully...but then nothing happens!! | 15:15 |
| latif | olofk: I know it is not an one -answered question but een so I am asking you: what could be the problem?? Or can you suggest me another tutorial?? I really want to see that I can do something with openrisc on FPGA.. | 15:18 |
| olofk | latif: I think there are some people in here who have been booting images from SPI Flash on Atlys just a few weeks ago | 16:35 |
| latif | olofk: do you know how can I connect them who are doing something about booting from spi flash?? maybe you know their names or something else?? | 18:28 |
| latif | olofk: is it possible to generate .mcs file by using fusesoc ?? | 18:36 |
| bandvig | Did you modify your rom.v in according with "Fixing the bootrom code " section in http://www.rte.se/blog/blogg-modesty-corex/writing-application-program/2.5 ? | 18:57 |
| latif | bandvig: thank you for your interest... yes i did what is said on the link.. | 19:16 |
| bandvig | latif: last chance: do ypu use latest version of orpsoc-cores with fusesoc? Old orpsoc-cores had got bug: the ROM's address width was smaller than required for spi boor rom. | 19:26 |
| latif | bandvig... i have tried with orpsocv2 | 19:57 |
| latif | I have tried it the tutorial on the link you have sent...so you mean they are not correct?? So, how can ı do it with v3?? | 19:59 |
| --- Log closed Sun May 03 00:00:33 2015 | ||
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