IRC logs for #openrisc Thursday, 2015-04-30

--- Log opened Thu Apr 30 00:00:29 2015
latifolofk: Why xilinix gives error when I add a bootrom.v file to your desing in orpsocv3??08:37
latifolofk: When I add a bootrom like here.. ..xilinix couldnot met timing.. how can I handle this??08:39
latifBy the way I am building for atlys by using fusesoc..08:40
olofklatif: Hmm... can you send over your .twr file so I can take a look at the timing report?09:36
olofkPull requests on github is a bit awkward. It would be nice if I could just clone the upstream repo and make my changes to that directly10:15
* olofk - git : 1-010:39
olofkIn the long run I'm probably way behind though :(10:39
olofk_franck_: I'm running wb_altera_ddr_wrapper against my updated wb_bfm-1.0. Jesus christ. Altera's free modelsim is insanely slow10:40
GeneralStupidolofk: do you have some (little and personal) Time for me?10:49
latifolofk:can you please wirte me your email adress so I can send you the .twr email is
stekernolofk: what do you mean "just clone the upstream repo and make my changes to that"? can't you?11:28
latifolofk: please have a look at this.. I 've pasted the orpsoc_top.twr file  here...
latifolofk: please have a look at this file.. orpsoc_top.twr
olofkstekern: No, I need to fork the repo first, then clone it and apply my patches there11:59
olofkBut I learned how to handle remotes now which makes it slightly less painful11:59
olofkGeneralStupid: Fire away your questions and I'll try to answer them in due time.11:59
olofklatif: According to that file you got a timing score 0, which means that it did meet timing12:00
latifolofk: but how?? xilinix couldnot generate bit file because of timing error ?? constarint did not met it says..12:06
latifahhh soryyy is not the rigth twr file so sorry..12:06
latifI will send over the rigth one so soryy about that..12:07
olofklatif: I will never forgive you12:24
latifolofk: you r rigth mann..but please wait a bit I am gonna send s being generated rigth now..12:28
stekernolofk: ah, right. but I just clone the upstream, do my changes and then push the fork button in github and push the changes there12:36
olofkstekern: Hmm... not sure I understand. Doesn't that require write access to the upstream repo?12:41
olofkstekern: Ahh.. ok12:42
olofkYou change origin in your cloned repo12:42
olofkOr whatever it's called in gitish12:43
latifolofk: xilinix has fnished its work but it did not generate a .twr file.. because it could not manage to implement the desing.. it says 2 constraints did not met. And it did not generate a .twr file?? Is taht normal not to generate .twr file??13:04
olofklatif: If it encountered an unroutable situation it will stop there before the timing analysis. Could that be what happened?13:07
olofkDo you have .mrp and .par files?13:07
latifthis is my place and route report..maybe it is helpful for you..
stekernyes, or just push to the other remote, which you seem to have learned about ;)13:09
olofklatif: Looks like it's the old Atlys dvi_clk problem. I think stekern has fixed this a few times13:10
latifolofk: this my mrp file...
stekernyeah, but that problem seems to be depending on the phase of the moon...13:12
latifolofk: this is the par file...
stekernif you don't absolutely need the hdmi output, disabling those parts of the design should solve it13:12
olofkI found four different bugs filed for this in orpsoc-cores and fusesoc :)13:14
latifstekern: hmm..but for my project may be I need it problem is with the eth_clock..  I think.. because xilinix did not met eth_clk constraint...13:14
olofklatif: No. Your problem is that it can't route the design due to a problem with dvi_clk13:15
olofkSeems to be some randomness in ISE that makes this problem pop up once in a while13:15
latifolofk: hmm..what about the comment part of the rom.v file?? I mean if I dont use bootrom there is a part in rom.v file.. I make it comment and then include bootrom.v there.. what is it if I dont use bootrom?? I mean what does that part do normally??13:18
latifif it is usefull for me I can use it instead of bootrom.v maybe :)13:19
GeneralStupidok, now something completely different :)13:26
GeneralStupidi have managed to compile a program with newlib, connected to my openrisc per jtag ... openocd seems to work and gdb too. But after continuing nothing happens :)13:27
latifGeneralStupidit:: Whats your program?? What do you want it to do??13:35
GeneralStupidlatif: the hello world which just prints a line13:36
latifok... I think you should have a gtk term program or something similar to see the output..13:37
GeneralStupidgtk term ok but iam new to this :)13:38
GeneralStupidi need or_debug_proxy?13:48
GeneralStupidwhere can i find a current version of the openrisc debug proxy?15:01
GeneralStupidreally guys, is it possible to get wiki write permissions or something? there are so many nice articles which are in nearly useless because of deadlinks15:11
-!- Netsplit *.net <-> *.split quits: ed-jones, tfh, pecastro, poke5328117:47
-!- Netsplit over, joins: tfh, poke5328117:49
_franck_olofk: so, is wb_altera_ddr_wrapper perfect ?17:54
_franck_GeneralStupid: you don't need gdb if you just want to execute a program. openocd can do that.17:55
_franck_load_image xxxx;reg npc 0x100;resume17:56
olofklatif: You will need some kind of boot ROM because OpenRISC must execute its instructions from somewhere when it boots up18:27
olofkBut we have been migrating away from the bootrom solution used in orpsocv218:27
olofkWell. That's not entirely true actually. You can connect to the CPU through JTAG, load up a program to RAM and set the PC that way18:28
olofkGeneralStupid: or_debug_proxy is deprecated since a few years. We use OpenOCD now. And to get access to the wiki I think you just need to register an account at opencores18:29
olofk_franck_: Not sure if it works actually. modelsim gave up after ~300 transactions, but that might actually be caused by some 32 bit counter that wraps around. The free modelsim version is really crappy18:31
GeneralStupid_franck_: i dont?20:24
GeneralStupidolofk: i will do so. Ok openocd is enough ... i need some documentation for openocd Thankyou20:25
GeneralStupidok does not work :( I dont know.  i can connect with telnet, i send the programm with gdb and run it, But there is no print21:27
GeneralStupidi have to learn the tools, if i halt i can see my message, continuing and halting again , i see the message again :) Nice21:31
olofkHmm... I'm porting the old SPI loader from orpsocv2 to be useful with wb_ram in FuseSoC, but I need to set the reset address to 0x104 to make it work properly21:58
olofkand looking at the code, I can't see that it would work any other way21:59
olofkjuliusb: How on earth is this thing supposed to work? :)22:06
olofkahh... could it be that bin2binsizeword doesn't add an instruction, but instead replaces the first instruction and assumes that it's not vital22:08
olofkah yes. Now it makes sense22:09
olofkok, so now I can simulate the SPI flash loading for the de0 nano system22:12
--- Log closed Fri May 01 00:00:30 2015

Generated by 2.15.2 by Marius Gedminas - find it at!