| --- Log opened Thu Apr 30 00:00:29 2015 | ||
| latif | olofk: Why xilinix gives error when I add a bootrom.v file to your desing in orpsocv3?? | 08:37 |
|---|---|---|
| latif | olofk: When I add a bootrom like here.. http://www.rte.se/blog/blogg-modesty-corex/writing-application-program/2.5 ..xilinix couldnot met timing.. how can I handle this?? | 08:39 |
| latif | By the way I am building for atlys by using fusesoc.. | 08:40 |
| olofk | latif: Hmm... can you send over your .twr file so I can take a look at the timing report? | 09:36 |
| olofk | Pull requests on github is a bit awkward. It would be nice if I could just clone the upstream repo and make my changes to that directly | 10:15 |
| * olofk - git : 1-0 | 10:39 | |
| olofk | In the long run I'm probably way behind though :( | 10:39 |
| olofk | _franck_: I'm running wb_altera_ddr_wrapper against my updated wb_bfm-1.0. Jesus christ. Altera's free modelsim is insanely slow | 10:40 |
| GeneralStupid | olofk: do you have some (little and personal) Time for me? | 10:49 |
| latif | olofk:can you please wirte me your email adress so I can send you the .twr file..my email is akcaylatif@gmail.com.. | 11:10 |
| stekern | olofk: what do you mean "just clone the upstream repo and make my changes to that"? can't you? | 11:28 |
| latif | olofk: please have a look at this.. I 've pasted the orpsoc_top.twr file here... http://pastebin.com/hhZfvGt9 | 11:37 |
| latif | olofk: please have a look at this file.. orpsoc_top.twr https://www.dropbox.com/s/kujw3esekjlqor8/orpsoc_top.twr?dl=0 | 11:42 |
| olofk | stekern: No, I need to fork the repo first, then clone it and apply my patches there | 11:59 |
| olofk | But I learned how to handle remotes now which makes it slightly less painful | 11:59 |
| olofk | GeneralStupid: Fire away your questions and I'll try to answer them in due time. | 11:59 |
| olofk | latif: According to that file you got a timing score 0, which means that it did meet timing | 12:00 |
| latif | olofk: but how?? xilinix couldnot generate bit file because of timing error ?? constarint did not met it says.. | 12:06 |
| latif | ahhh soryyy mann..it is not the rigth twr file so sorry.. | 12:06 |
| latif | I will send over the rigth one so soryy about that.. | 12:07 |
| olofk | latif: I will never forgive you | 12:24 |
| latif | olofk: you r rigth mann..but please wait a bit I am gonna send it..it s being generated rigth now.. | 12:28 |
| stekern | olofk: ah, right. but I just clone the upstream, do my changes and then push the fork button in github and push the changes there | 12:36 |
| olofk | stekern: Hmm... not sure I understand. Doesn't that require write access to the upstream repo? | 12:41 |
| olofk | stekern: Ahh.. ok | 12:42 |
| olofk | You change origin in your cloned repo | 12:42 |
| olofk | Or whatever it's called in gitish | 12:43 |
| latif | olofk: xilinix has fnished its work but it did not generate a .twr file.. because it could not manage to implement the desing.. it says 2 constraints did not met. And it did not generate a .twr file?? Is taht normal not to generate .twr file?? | 13:04 |
| olofk | latif: If it encountered an unroutable situation it will stop there before the timing analysis. Could that be what happened? | 13:07 |
| olofk | Do you have .mrp and .par files? | 13:07 |
| latif | this is my place and route report..maybe it is helpful for you.. https://www.dropbox.com/s/hed0wptlfkr5ucg/place%20and%20route%20report?dl=0 | 13:07 |
| stekern | yes, or just push to the other remote, which you seem to have learned about ;) | 13:09 |
| olofk | latif: Looks like it's the old Atlys dvi_clk problem. I think stekern has fixed this a few times | 13:10 |
| latif | olofk: this my mrp file... https://www.dropbox.com/s/pxqmb82ac1zvmg8/orpsoc_top_map.mrp?dl=0 | 13:10 |
| stekern | yeah, but that problem seems to be depending on the phase of the moon... | 13:12 |
| latif | olofk: this is the par file... https://www.dropbox.com/s/z02ov9tg4rdq5ke/orpsoc_top.par?dl=0 | 13:12 |
| olofk | latif: https://github.com/openrisc/orpsoc-cores/issues/77 https://github.com/openrisc/orpsoc-cores/issues/82 | 13:12 |
| stekern | if you don't absolutely need the hdmi output, disabling those parts of the design should solve it | 13:12 |
| olofk | I found four different bugs filed for this in orpsoc-cores and fusesoc :) | 13:14 |
| latif | stekern: hmm..but for my project may be I need it later..my problem is with the eth_clock.. I think.. because xilinix did not met eth_clk constraint... | 13:14 |
| olofk | latif: No. Your problem is that it can't route the design due to a problem with dvi_clk | 13:15 |
| olofk | Seems to be some randomness in ISE that makes this problem pop up once in a while | 13:15 |
| olofk | gtg | 13:15 |
| latif | olofk: hmm..what about the comment part of the rom.v file?? I mean if I dont use bootrom there is a part in rom.v file.. I make it comment and then include bootrom.v there.. what is it if I dont use bootrom?? I mean what does that part do normally?? | 13:18 |
| latif | if it is usefull for me I can use it instead of bootrom.v maybe :) | 13:19 |
| GeneralStupid | ok, now something completely different :) | 13:26 |
| GeneralStupid | i have managed to compile a program with newlib, connected to my openrisc per jtag ... openocd seems to work and gdb too. But after continuing nothing happens :) | 13:27 |
| latif | GeneralStupidit:: Whats your program?? What do you want it to do?? | 13:35 |
| GeneralStupid | latif: the hello world which just prints a line | 13:36 |
| latif | ok... I think you should have a gtk term program or something similar to see the output.. | 13:37 |
| GeneralStupid | gtk term ok but iam new to this :) | 13:38 |
| GeneralStupid | i need or_debug_proxy? | 13:48 |
| GeneralStupid | where can i find a current version of the openrisc debug proxy? | 15:01 |
| GeneralStupid | really guys, is it possible to get wiki write permissions or something? there are so many nice articles which are in nearly useless because of deadlinks | 15:11 |
| -!- Netsplit *.net <-> *.split quits: ed-jones, tfh, pecastro, poke53281 | 17:47 | |
| -!- Netsplit over, joins: tfh, poke53281 | 17:49 | |
| _franck_ | olofk: so, is wb_altera_ddr_wrapper perfect ? | 17:54 |
| _franck_ | GeneralStupid: you don't need gdb if you just want to execute a program. openocd can do that. | 17:55 |
| _franck_ | load_image xxxx;reg npc 0x100;resume | 17:56 |
| olofk | latif: You will need some kind of boot ROM because OpenRISC must execute its instructions from somewhere when it boots up | 18:27 |
| olofk | But we have been migrating away from the bootrom solution used in orpsocv2 | 18:27 |
| olofk | Well. That's not entirely true actually. You can connect to the CPU through JTAG, load up a program to RAM and set the PC that way | 18:28 |
| olofk | GeneralStupid: or_debug_proxy is deprecated since a few years. We use OpenOCD now. And to get access to the wiki I think you just need to register an account at opencores | 18:29 |
| olofk | _franck_: Not sure if it works actually. modelsim gave up after ~300 transactions, but that might actually be caused by some 32 bit counter that wraps around. The free modelsim version is really crappy | 18:31 |
| GeneralStupid | _franck_: i dont? | 20:24 |
| GeneralStupid | olofk: i will do so. Ok openocd is enough ... i need some documentation for openocd Thankyou | 20:25 |
| GeneralStupid | ok does not work :( I dont know. i can connect with telnet, i send the programm with gdb and run it, But there is no print | 21:27 |
| GeneralStupid | ahh | 21:30 |
| GeneralStupid | i have to learn the tools, if i halt i can see my message, continuing and halting again , i see the message again :) Nice | 21:31 |
| olofk | Hmm... I'm porting the old SPI loader from orpsocv2 to be useful with wb_ram in FuseSoC, but I need to set the reset address to 0x104 to make it work properly | 21:58 |
| olofk | and looking at the code, I can't see that it would work any other way | 21:59 |
| olofk | juliusb: How on earth is this thing supposed to work? :) | 22:06 |
| olofk | ahh... could it be that bin2binsizeword doesn't add an instruction, but instead replaces the first instruction and assumes that it's not vital | 22:08 |
| olofk | ah yes. Now it makes sense | 22:09 |
| olofk | ok, so now I can simulate the SPI flash loading for the de0 nano system | 22:12 |
| --- Log closed Fri May 01 00:00:30 2015 | ||
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