IRC logs for #openrisc Friday, 2015-03-20

--- Log opened Fri Mar 20 00:00:29 2015
olofkI found a bug in wb_ram btw that broke it for back-to-back bursts12:26
olofkI think stekern pointed this out ages ago, but I forgot to follow it up12:26
olofkAnyone got some knowledge of SD card standards? Trying to figure out how much of the protocol that is done in software and hardware12:27
_franck_olofk: I know it a bit12:36
_franck_look here it explains the basics:
_franck_and this is interresting:
olofk_franck_: Thanks.12:48
olofkoh... I got a mail12:48
olofkIt says 'ping' :)12:48
olofkSorry _franck_12:48
_franck_that's the last thing to make my verilator_or1ksim_wb_master to work with upstream fusesoc12:50
olofk_franck_: I'll try to remember to do it tonight13:33
_franck_olofk: if you are curious and have some time you can try my verilator/or1ksim branches on github16:30
_franck_it is fusesoc systemc_bench branch and orpsoc-cores systemc16:31
_franck_then python3.4 ./bin/ --verbose sim --force simple_spi --vcd should give you a vcd16:31
-!- pecastro_ is now known as pecastro17:24
--- Log closed Sat Mar 21 00:00:31 2015

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