IRC logs for #openrisc Tuesday, 2015-02-17

--- Log opened Tue Feb 17 00:00:44 2015
stekernI just pushed my close to done lk port here:
stekernthe only thing left to do is to clean up the uart code02:51
stekernseems like there are about 5-6 different drivers for ns16550 in the tree02:52
stekernand I'm adding yet another02:52
sheridp1Hello, I have a question about addressing in the open risc. I'm using the altor32, and see that the boot_vector is at h10000000 but the ram in the examples is only 24KB04:06
sheridp1A lot of the example code has origin at 0x10000000; is there something I'm missing? with 24KB and 32bit wide, there would only be 6000 addresses04:07
stekernsheridp: is that altor32 example code you're referring to?05:59
olofkstekern: I see that you were also enlightened by the segfault PC question on the mailing list :)07:15
olofkAnd cool stuff with lk. That deserves a tweet and beer!07:16
olofksheridp: Yes, it probably only uses a few hundred addresses, but the base address is 0x10000000, so it isn't using anything below that07:17
olofkantgreen: Have you considered using 32-bit buses for instruction and data? Most Wishbone peripherals are 32-bit so it would make it easier to use those straight away07:53
_franck_olofk: I read your post on the forum about how to modify the core for tests08:35
_franck_don't you think it's too complicate and we should find a way to make it easier ?08:36
_franck_if you edit the core in ./build and don't use --force it should work right ?08:36
olofk_franck__: If you remove --force it won't rebuild the simulation model08:57
olofkAnd yes, it's a bit complicated, but not _that_ complicated. It's just to get the sources, copy the core file and remove the provider section08:58
olofkBut if you have ideas for how to make it easier I'm interested in knowing08:58
_franck_I don't for now :)09:01
_franck_newlib toolchain compiled under MSYS209:31
_franck_c++ disabled because it generates an internal gcc error while compiling09:32
olofk_franck__: Cool! I was actually wondering about windows support earlier today. I'm stuck on a Windows machine while my computer is on repair09:35
olofkIt's a fucking nightmare to get things done09:35
GeneralStupidgcc is not a c++ compiler... is there something wrong with the makefiles?09:37
_franck_gcc sources generate g++ if configured to do it09:38
wallento_franck_: is the or1k stuff upstream in openocd? sorry, I somehow lost track of this..10:01
olofkwallento: Yes. I used upstream 0.8.0 just a while ago10:43
olofkI would like to clean up the OpenRISC repos on github. OpenOCD would be a good candidate to remove if everything is upstream10:45
olofkPerhaps do the same thing with newlib once the next snapshot is released10:46
olofkIf we are going to add stuff in the future, I guess we would clone upstream directly anyway10:46
_franck_^ this is not upstream10:54
_franck_but I could keep this in my own github10:54
_franck_because I don't think I'll ever upstream it10:54
stekernolofk: I'll polish the port some more and then propose it 'upstream', I'm still ~a week here so hope to get it done before that10:55
stekernwe're switching places tomorrow too, hopefully there is  better internet connection there10:56
stekern.. just so you can plan for some more beer I mena10:56
stekernI just downed a chang in the sunset here, hence the typos ;)10:57
stekern_franck_: cool, reminds me that we should probably sync to 4.9.211:13
olofkstekern: Nice. The weather in this part of the world sucks right now so don't rush back here :)11:21
olofk_franck__: Is it only line 38 that is not upstream?11:21
n0bawkhello, I would like to try some external peripheral for or1ksim, however, I do not see it call the upcall interface. Would you please help me?11:46
n0bawkthis is my code11:47
Akiraahow difficult would it be to implement the "mass storage device" API (or equivalent) for a programmable device like 'banana pi' or olinuxino or similar boards?11:47
n0bawkand this is my sim.cfg:
AkiraaI would be interested even in some useful keywords for search if you can help (implementing USB "mass storage device" from a linux box with USB-OTG)11:56
wallentoolofk: I would keep a newlib repo on our organization. the docu can of course move to, but at the moment there are still a few features I plan to add. mainly MMU configuration12:18
olofkn0bawk: Sorry. Haven't used the or1ksim lib, but there should be others here who would know it better12:24
olofkwallento: Yes. That makes sense then if we have some kind of development planned for it12:25
wallentodidn't really proceed with getting openocd to know there are two cores behind a tap12:26
n0bawkolofk: I am trying to model a SoC using TLM; however, I am not sure why the upcall does not work :(12:29
n0bawkI am trying to write data into the memory region defined in a generic section12:30
olofkn0bawk: I know that _franck__ did some experiments with embedding or1ksim in a verilator simulation. He might know12:31
_franck_^ it works for me12:33
_franck_olofk: what is not upstream in our github openocd is the classic debug interface a.k.a Mohor12:33
olofk_franck__: Ah ok. Yeah. It could be good to have around, but the new interface should be enough to have upstream12:35
n0bawk_franck_: with your configuration it works, but with mine it does not12:38
_franck_you have the same base address as the uart12:39
_franck_try something else12:39
_franck_oh it's disabled12:39
n0bawkhmmm, I tried with 0xA0000000 also12:40
_franck_but try something else as a base address for the generic section, we never know12:40
_franck_ah ok12:41
_franck_well, shrink your cfg file to a minimum, then compare it to mine12:42
n0bawkso the problem is the configuration file12:44
n0bawkI disable other sections (left only the cpu and generic) and it works12:48
n0bawkIf I enable the mc section, it will not work12:52
_franck_never used this section, need to check the manual :) I can't help you12:55
_franck_welcome to openrisc, now please open or1ksim source code and find why it doesn't work :)12:56
rschmidlinHi, I have implemented the mor1k-generic design on an artix-7. Hello world worked fine. But when I try to turn on the caches I get an exception. Weirdly, the simulation runs to the end. Anyone has an idea of what might be going on?13:03
rschmidlinI was considering configuring MIG for my system and using what is available from the atlys system. But it seems that the mig interface has changed somewhat.13:05
olofkrschmidlin: Xilinx MIG is horrible. The interface is different between every version, every product family and dependning on if you generate verilog or VHDL13:13
n0bawk_franck_: thank you13:24
rschmidlinOlofk, a real pity. I still don't know why I get the exception on the block rams. :(14:08
olofkjeremybennett: You around?14:47
olofkrschmidlin: Are you using wb_ram as your memory?14:58
Me1234_olofk: In this guide openocd is mentioned:
Me1234_Or is this older openocd15:09
Me1234_olofk: ?15:09
rschmidlinOlofk, yes, ram_wb_b3.v15:19
jeremybennettolofk: I am15:20
Me1234_olofk: I see that actually openocd works with orpsocv2, but the example timerled from orconf2013 repo loops somewhere around 0x00003544 in or1k_cache_init ().15:46
Me1234_olofk: Wrong newlib?15:46
Me1234_olofk: Orpsoc v2 works with old openocd, which i found on one of my virtual PCs, which, I think, has been downloaded from
olofkjeremybennett: Do you have any more of your fancy USB-to-UART adapters?17:04
olofkrschmidlin: ram_wb_b3 isn't really synthesisable17:04
olofkMe1234_: Ah yes. That's for a real target. I thought we were talking about simulations17:05
olofkrschmidlin: wb_ram should work though17:07
olofkDifferent things :)17:07
olofkHmm... I got a feeling that we talked about this before17:07
rschmidlinOlofk, I don't know yet which part of it isn't. But I will take a look at it tomorrow. I'm also finally looking for a possibility to log to irc from work.17:17
olofkrschmidlin: I think you can use a web interface to connect if you can't connect directly17:51
olofkMe1234_: Looping in the cache init does sound wrong. Haven't got any explanation though17:59
-!- julzmb_ is now known as julzmb18:20
Me1234_olofk: Looping in the cache init happens only with new openocd.18:29
olofkMe1234: What? Just changing the OpenOCD version?19:27
Me1234olofk: Wait. I will check again.19:45
Me1234olofk: I do not know. I cannot reproduce the error now. I will try later. I have no time19:49
Me1234Now I have working linux booting from spi flash on de0_nano with orposc v219:50
olofkMe1234: That's good to know! SPI flash booting is one of the remaining things I haven't taken care of yet for the new OpenRISC systems19:57
Me1234olofk: It is an old openrisc system: orpsoc v2.20:06
olofkMe1234: Yeah, but it's good to know that it's working there, so I don't start porting something that is broken :)20:09
olofkWhat the...? Downloaded a zip file from Spansion that should contain a verilog model. Inside the zip is a .exe file22:10
olofkI'm not going to compile Wine for this22:11
olofkAny Windows user around who can tell me what the exe in this archive does?
olofkAha! Found it on Free Model Foundry instead22:18
--- Log closed Wed Feb 18 00:00:46 2015

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