IRC logs for #openrisc Monday, 2015-02-16

--- Log opened Mon Feb 16 00:00:43 2015
wallento_franck_: did you have a look at the multicore openocd topic?09:42
poke53282stekern: Nope, everything on my harddrive.09:58
poke53282But the changes in the end were minor. Just take the repository from blueCmd.09:59
poke53282You don't get anything new by using the newest QEMU version.09:59
_franck_wallento: a loooong time ago. Long enough to forget everything I would have learnt10:46
_franck_but I think it wasn't that hard10:46
wallento_franck_: thanks, I will have a look at it15:13
Me1234Why does neither old orpsoc nor mor1kx-dev-env work with gdb, openocd even with timerled examlple from orconf 2013 repo, not to mention linux16:22
Me1234Where can i get orpsoc v216:57
-!- Netsplit *.net <-> *.split quits: stekern, ysionneau, jonmasters17:25
Me1234found it, git is a good thing, yo can always revert changes you made.17:31
-!- Netsplit over, joins: ysionneau, stekern, jonmasters17:31
olofkMe1234: ORPSoCv2 used another way to interact with GDB than the current systems in orpsoc-cores17:48
olofkAnd I'm not sure about mor1kx-dev-env. That hasn't been maintained for quite a while17:48
olofkWhat the hell is gecko03?19:24
olofkGoogle gives me results from everything from Austrian childcare, motorbikes, German books and muslim news sites19:26
olofkok, found it19:29
olofkGreat. It uses MicroBlaze19:30
olofk_franck_: Your extra files FuseSoC patch is awesome btw. I have already found several places where I want to use it19:39
Me1234olofk: you mean adv_debug_sys?20:08
sheridpDoes anyone know how to embed an elf into BRAM for a Xilinx FPGA? I'm trying to replace the bootloader in AltOR3220:11
olofkMe1234: Not really. In ORPSoCv2 we had a VPI module that implemented a GDB server and translated that to JTAG, so you connect GDB directly to that. The method we use now is that we have a a small VPI module that OpenOCD connects to with the jtag-vpi driver, so that we can reuse the GDB server from OpenOCD instead. Less code to maintain for us and more like the real hardware workflow20:21
olofksheridp: I have done that with MicroBlaze ELF files, but in that case objdump could create the correct format directly. For AltOr32 I guess you need to create a bin file and then convert that to a format that the Xilinx tools can recognize. Then there's the step of actually loading it. Is it an option to use wb_ram instead? In that case I can help you with scripts that turns an assembly file into something that can be loaded into the boot RAM20:24
olofkBut since you are using AltOr32 instead of mor1kx or or1200 I presume you want to keep it VHDL only. Is that right?20:25
sheridpwb_ram would be great. Actually I prefer verilog, and am not even really stuck on the altor32; I just need something that can fit into a spartan6 lx920:29
olofksheridp: I have a half-finished port for the LX9 MicroBoard with mor1kx20:31
sheridpI see that on your github, is that up to date?20:33
olofksheridp: I haven't done any work on it after I put it on github. IIRC I got the led_blink bootloader working, but since I never connected the Flash, I didn't run any software on it20:58
olofkI will probably work on it a bit in three weeks20:59
olofkAnd the first thing to do then will probably be to connect the Flash and port the SPI bootloader from ORPSoCv220:59
sheridpolofk:Thanks, I'm going to fork it and try to get it running on my system (a mojoV3)21:00
olofkCool. Let me know if I can help you with anything21:01
olofkWill you use FuseSoC btw?21:01
olofkThe Mojov3 looks nice21:02
sheridpolofk: Yes, I'm just finding out about fusesoc today, but I will try to figure it out21:02
olofkDon't hesitate to ask for help. It still has some rough edges... like no documentation whatsoever :)21:04
sheridpolofk:  I think it's a pretty similar question that I had earlier, how does fusesoc get the elf file into the fpga config bit file?21:14
olofksheridp: You convert an assembly files via a bin file to a file that the verilog $readmemh command can parse. Then you set the memfile paramter of wb_ram to your generated .vh file21:24
olofkDamn. I thought I had pushed my collection of tiny bootloaders to github. hmm... where are they21:26
olofkOh well. I'll find it.21:27
sheridpwith readmemh being in an initial block, does that get executed when you synthesize for actual hardware or only for simulation?21:27
olofkThat works for synthesis as well. That method is actually part of the verilog substandard for syntheisizable RTL21:28
sheridpah, excellent I did not realize that21:29
olofkIt's pretty neat. The biggest problem I have had is that I haven't been able to write wb_ram in a way that it's vendor agnostic, maps well against FPGA resources and can be preloaded at the same time21:30
olofkSo I intend to push a wb_rom to be used for bootloaders and drop the preinitialization from wb_ram, because it just won't work reliably on Altera devices21:32
sheridpHow is the performance of wb_ram? Does having other peripherals on the bus slow execution?21:33
olofkIt's very quick since it's just using small on-chip RAM. If you have a shared data/instruction bus it will probably be slowed down if you try to access some peripheral on the data bus and read instructions from wb_ram, but that shouldn't be an issue21:37
olofkYou will most likely only execute a handful of instructions from it and then load a real application into your main RAM21:38
sheridpOh I see, I thought the wb_ram was to serve as the main RAM21:39
olofkNo. Just as a rewritable boot loader, or if you need a small superfast memory area21:39
olofkhmm... I can't see any RAM on the Mojov321:40
sheridpNo there's not any. You have to add it externally21:43
olofkIn that case it will be your main RAM as well, but you will only have at most ~70KB RAM21:43
olofkaha. I see the SDRAM shield now21:44
olofkI guess the intention is to run sw in the MCU instead, but what fun is that? :)21:47
sheridpYes, its21:48
sheridpactually someone annoying because there is only a serial bus connecting the two21:48
olofkEvery FPGA deserves to have an OpenRISC in it!21:48
--- Log closed Tue Feb 17 00:00:44 2015

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