IRC logs for #openrisc Sunday, 2015-02-15

--- Log opened Sun Feb 15 00:00:42 2015
stekernseems like I keep missing that mel1234 guy all the time...01:03
stekernpoke53282: you around?03:21
stekerndo you have your qemu changes somewhere public?03:21
-!- Netsplit *.net <-> *.split quits: julzmb, arokux09:31
-!- Netsplit over, joins: arokux09:32
olofkHas anyone played with yosys for OpenRISC stuff? Interested in having it as an alternative synth flow in FuseSoC11:40
stekernnope, but I've thought about looking into it, so I'm interested if you take it for a spin13:37
stekerndid we have a hack to read uart input with verilator for fusesoc or was that only for the old orpsocv2 one?13:43
Me1234Seems that opencores svn does not work.17:26
Me1234fusesoc hang for a while and then exits with error17:27
Me1234INFO:  Preparing uart1655017:27
Me1234INFO:  Checking out http://opencores.org/ocsvn/uart16550/uart16550/trunk revision 108 to /root/.cache/fusesoc/uart1655017:28
Me1234svn: E000110: Unable to connect to a repository at URL 'http://opencores.org/ocsvn/uart16550/uart16550/trunk'17:28
Me1234svn: E000110: Error running context: Connection timed out17:28
Me1234ERROR: Failed to configure the system17:28
Me1234ERROR: "svn co -q --no-auth-cache -r 108 --username orpsoc --password orpsoc http://opencores.org/ocsvn/uart16550/uart16550/trunk /root/.cache/fusesoc/uart16550" exited with an error code.17:28
Me1234ERROR: See stderr for details.17:28
sheridpHello; Has anyone had a problem with running the makefile in AltOR32?17:44
olofkstekern: I remember some work on UART input in verilator, but can't recall the details20:31
--- Log closed Mon Feb 16 00:00:43 2015

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