IRC logs for #openrisc Saturday, 2014-10-04

--- Log opened Sat Oct 04 00:00:22 2014
olofkI think I got quartus to load the memory init file now by removing the bytewise write enables08:31
olofkI guess that's ok for a bootloader ROM/RAM, but it's not very nice if we want to use it as a small generic ram08:32
olofkDoes anyone know if the Altera primitives support byte-size write enables? The Xilinx ones do08:34
olofkIf so, I should probably do an altera-specific wb_ram backend08:34
olofkCan I see where an exception was triggered with gdb?08:36
olofkLike, which was the last pc address before entering the exception vector08:37
stekernolofk: epcr09:41
poke53282The timing in JavaScript is so bad. I have added around 150 lines of logic just for the timing. But I believe somehow it get worse.16:50
olofkstekern: How do I get epcr? It wasn't in info all-registers19:27
olofkAha... simulations helped me find the problem19:59
olofkMismatch between wb_ram parameters and wb_intercon settings20:00
olofkI really need to split out those params to a separate file20:00
olofkWhat the hell is wrong with those leds? Simulations show that they blink20:02
olofkahh. they do blink20:03
--- Log closed Sun Oct 05 00:00:23 2014

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