IRC logs for #openrisc Tuesday, 2014-04-08

--- Log opened Tue Apr 08 00:00:55 2014
stekernLimb: so, do you have an .ucf file, connecting your top module to the outer world?03:07
stekern...ah, missed that link, so yes you do03:07
stekerndon't know if it's the answer, but the connection here should be wb_rst instead of wb_rst_i:
stekernthen there's fun messages like this:
stekernwhich I don't really understand why it does03:46
Limbstekern: I have a feeling its removing my port connections... but I don't have a clue why05:05
Limbis there any sort of reference on what clock speeds I need to be generating? does it even matter?05:07
stekernno, I don't think so, it seems like it's already throwing everything away at synthesis stage05:08
stekernI'm as confused as you on this05:08
stekernone thing we could try is to connect the sys_clk_pad_i directly to wb_clk, to rule out that it's something in clkgen.v that makes that clock path go away05:09
LimbI've tried a thousand variations05:10
LimbI tried that as well05:10
stekernthere's a lot of MACRO stuff going on there, might be that something is spartan6 specific05:10
stekernoh, ok05:10
Limbfrom what I could find, it seems to be eliminating the connections because it thinks they are null05:11
Limbbut I don't see why it is... the connections are valid05:11
Limbdo I need to include a debug module no matter what?05:12
stekernwhat if you change the part to spartan6?05:12
stekern(i.e. the same as it was in the atlys board)05:12
stekernwell, you should really connect the signals to _something_, but since they will default to 0, I doubt that's an issue05:13
Limbstekern: what's your usual active times?05:27
stekernas in when I'm awake?05:27
stekernusually between 05:30 - 23:00 EEST05:31
stekernchanging the part to spartan6 didn't change things05:32
LimbI meant when you were awake yes :) seems between you and olofk, I'm available during your off times he he05:36
LimbI don't have access to my PC right now. I'm hoping I can catch you in ~8 or 9 hours05:37
Limbis it possible I'm not setting a connection on the CPU correctly? I was messing with the clock gen and it seems to be the only thing that actually gets synthesized05:39
stekernas far as I can see, everything is connected as it should...05:39
stekernI did a diff between the atlys orpsoc_top.v and the nexys4.v and everything that matters are connected the same way05:40
stekernI'll swap into my old ISE builder to see if that would make a difference, but that's just a shot in the dark05:40
LimbI was basing my code heavily on the atlys. as far as I can tell in terms of the bare minimum there shouldn't be much of a difference between them05:41
Limbbut I tried basing it off the mor1k-generic as well05:42
Limbevery idea results in the same blank generation05:42
Limbthe most I can get is the clock gen gets implemented that's it05:44
stekernthere got to be some small stupid detail we are overseeing05:46
LimbI tried everything I could think of. I don't see why it wants to think nothing exists05:52
stekernyeah, it's crazy...05:59
olofk_Limb: If you send over your .syr file from the synthesis, I can take a look at that06:22
stekernthat has sys_clk_pad_i and rst_n_pad_i directly connected to wb_clk and wb_rst06:32
stekernoh, and I have hacked your wb_ram a bit, since I don't trust those $clog06:39
olofk_stekern: I have rewritten most of the stuff in wb_ram. That was just the latest commit that worked :)06:41
olofk_But yes. I forgot about XST's clog2 problem, so it's probably good to have that rewritten anyway06:42
stekernyeah, I just took away all notion of depth and fed the address width instead06:48
stekernI think that makes more sense for a RAM06:48
stekernand a hint, don't connect stb_i to ack_o ;)06:50
stekernI bet that's just copy-paste from ram_wb06:50
olofk_stekern: ram_wb ws surprisingly messy when I looked at it. A few naughty latches as well that I have taken care of since07:05
stekernyup, I can't imagine that a cleaned up version would take more than ~20 lines of code07:12
stekernminus port declaration and block ram instantiation07:13
stekernmaybe I meant plus in that sentence07:24
olofk_I'm not getting any wiser with the synthesis stuff. It warns that wb_clk_o, wb_rst_o, async_rst_o and clk100_o has no loads, and I can build the clock generation stand-alone07:40
olofk_But uart0_stx_pad_o is the only output, so if synthesis determines it's static I guess it could remove everything07:42
stekernit's just strange07:47
olofk_I think the wishbone spec could need some clarifications08:22
olofk_Should a burst-compatible slave only register address on the first word and use cti/bte to calculate next address?08:23
stekern...but as always, all strange things have a natural explanation:
stekernregister address?08:28
stekernyou mean use?08:31
stekernno, all accesses are bound to the incoming address08:31
stekerni.e. it's not like avalon, where you ive a start address08:31
olofk_(uart) Yes. We should really change that to a parameter and throw away that stupid defines file... or get ourselves a new uart08:32
olofk_I started doing some define to parameter conversion, but I realized quite early that it would need quite large changes08:35
stekernso, for your wb_ram, since all accesses are 1-cycle, all you really need to do is: always @(posedge clk) wb_ack_o <= wb_stb_i & wb_cyc_i & !(classic | end_of_burst)08:41
stekernfor burst accesses08:41
stekernalways @(posedge clk) wb_ack_o <= wb_stb_i & wb_cyc_i & (!(classic | end_of_burst) | !wb_ack_o);08:43
stekernshould cover everyting08:43
stekern..nah, not quite, the end_of_burst will be wrong, but you get the point hopefully08:46
olofk_Where classic = (wb_cti_i = 3'b000) and end_of_burst = (wb_cti_i = 3'b111)?08:46
olofk_s/=/== :)08:46
stekernor, no, maybe that's right... you are already acking the end_of_burst when you get wb_cti_ = 3'b11108:47
stekernhard to write code in IRC ;)08:47
stekernyes, 3'b000 is classic and 3'b111 is end_of_burst08:47
stekernyou will of course need to still calculate the next address on bursts, since that's what you are hooking up to the block RAMs address port08:49
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--- Log closed Tue Apr 08 10:26:43 2014
--- Log opened Tue Apr 08 10:27:02 2014
-!- Irssi: #openrisc: Total of 30 nicks [0 ops, 0 halfops, 0 voices, 30 normal]10:27
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amswhy ...10:28
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olofk_stekern: wb_ram.v is about 20 lines now as you said10:53
olofk_blueCmd: pastebin because doesn't have verilog syntax highlighting10:56
olofk_I need to expand the BFM transactors to generate classic cycles as well. They are quite handy, but they aren't checking everything10:57
olofk_And to be honest, I don't trust them completely, as I wrote them :)10:57
olofk_Just stumbled upon f-cpu, the freedom CPU. Can't find any code, but an incredibly ugly homepage :)
stekernyou can get it down to even fewer lines if you remove the excessive empty ones ;)11:09
stekernand 'reg wb_ack_o_r;'11:09
stekernthat homepage look all the rage, considering it was made in 200111:12
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Limbso it looks like i have a mystery on my hands if you two can't figure out what I've messed up haha14:07
Limb.... you're kidding me14:16
Limbstekern: how on earth did you figure out that uart line would fix it14:16
amsstekern is god.14:18
Limbof course now I get ERROR:MapLib:1209 - Retargeting of PLL clkgen0/pll0 has COMPENSATION attribute14:19
Limb   is set to DCM2PLL or PLL2DCM. This is not supported yet in the tools to14:19
Limb   target a single MMCM. To enable an unoptimized retargeting please set14:19
Limb   XIL_MAP_NO_PLL2MMCM_COMP_ERROR environment variable.14:19
Limberrr sorry for the multi-lines. thought that would paste as one line :X14:19
LimbHow do I know exactly what clocks I need to generate?14:20
olofk_This will have to do
Limbolofk: Can I plop that in the previous code you gave me?14:29
olofk_Limb: The line breaks in Xilinxs log file has annoyed me for many years. Those incompetent idiots just won't fix it14:29
olofk_Limb: Probably no. You need an extra file as well14:29
LimbI figured hehe14:29
Limbolofk: did you ever implement the xilinx ram method?14:30
LimbSaw you had some code for it14:30
olofk_Limb: Yes. The code I just pasted will be implemented as Block RAM (at least on Spartan6)14:30
Limbwell I've got a bit file14:37
Limbnow I need to figure out how to compile a program and upload it lol14:37
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stekernit was what olofk said about the uart being the only output and a line in the synthesis report complaining about bit 1:0 in the uart addr being unconnected that got me on that track15:06
Limbstekern: you rock :)15:11
* Limb has uploaded the bitfile to the board finally \o/15:11
Limbbut now I haven't a clue what to do lol15:11
LimbAnyone have a guide on how to create a simple program and upload it?15:25
stekernI've used an external jtag adapter and ethernet to upload to the atlys board15:29
stekernit should be possiböe to use the internal jtag tap of the fpga too, and use the existing usb port, but I never tried that15:30
Limbso theres no way to include the program in the bitfile? i'll have to do it manually?15:32
stekernyou can of course preload the block ram16:07
Limbstekern: how would i go about doing that exactly?16:08
stekernas olofk have been experimenting, you can use $readmemh to initialize a blockram16:12
stekernthinking this l.lwa/l.swa stuff through a bit right now, I wonder how it would make most sense to indicate that a store conditional have failed18:53
stekernI'm thinking about perhaps set/clear the flag bit in SR18:54
stekernbecause that would make it easy to conditionally jump right after store conditional18:54
stekernmicroblaze sets the carry flag18:55
stekernthe flag bit is a critical path in mor1kx, so it might be a bad idea to hook up additional logic to that19:01
stekernmips on the other hand set the result in the source register19:03
Limbhas anyone used the xilinx virtual JTAG with advanced_debug_sys?19:28
stekernLimb: I think _franck_ mentioned that someone had19:47
_franck_Limb: yes someone did that with openocd20:03
Limbcan't find a thing on how to even access the JTAG output hah20:03
_franck_you need to instanciate the Xilinx virtual JTAG tap (never used it myself) then connect it to advanced debug interface20:06
_franck_Limb: look here:,filedetails?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2Fverilog%2Fminsoc_top.v20:10
_franck_look at how the altera vjtag is hooked up here
_franck_and replace it with minsoc_xilinx_internal_jta from the minsoc project20:11
_franck_that might work :)20:12
blueCmdstekern: olofk:
LimbblueCmd: thats running on a risc?22:57
LimbI can't find a single piece of documentation on this internal jtag thing -_-23:28
--- Log closed Wed Apr 09 00:00:57 2014

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