IRC logs for #openrisc Monday, 2014-04-07

--- Log opened Mon Apr 07 00:00:54 2014
analognoiseHey Openrisc00:33
LimbStill no ISE system cores yet?01:10
LimbTraceback (most recent call last):02:00
Limb  File "/usr/local/bin/fusesoc", line 14, in <module>02:00
Limb    from import BackendFactory02:00
Limb  File "/usr/local/lib/python2.7/dist-packages/fusesoc/build/", line 2, in <module>02:00
Limb    from import Ise02:00
LimbImportError: No module named ise02:00
LimbGetting that with the latest git pull build02:00
stekernLimb: by the pull request, I reckon you already figured out what was wrong ;)03:06
LimbHaha yep :)03:20
Limbstekern: Do you by chance have a example ISE project you can share?03:20
Limbsaw olofk was saying you might yesterday03:21
LimbTrying to adapt one on my own.. but I also don't have a clue what I'm doing haha03:21
stekernLimb: yeah, I'll push my atlys project soon, it'll need some minor adjustments to olofk's ise backend, it's slightly different than mine03:32
stekernmy work-in-progress on it is available here though:
LimbThats a lot of work haha03:36
Limbhope itll be relatively easy to port to a Nexys403:37
stekernwhat kind of memory does it have?03:38
stekernah, ok03:39
LimbThat good or bad? haha03:39
stekernso same as the "old" nexus303:39
LimbI believe so03:39
stekernit's probably fine, if it's the same as nexus3, you should be able to pull the memory controller wrapper for the orpsocv2 nexus3 board into your port03:40
LimbIs there any place that defines the bare minimum cores you need to get a processor up and running?03:41
stekernwell, the or1200-generic and mor1kx-generic systems are pretty much that03:42
stekernsome kind of RAM, cpu and uart is basically all you need03:42
stekern(of course you don't *need* to have the uart, but it's nice to get some feedback ;))03:43
LimbI'm hoping it won't be too hard03:44
LimbAny specific difference between ork1200 and mor1kx?03:45
stekernLimb: or1200 is the original implementation. mor1kx is a newer implementation, that tries to correct some deficiencies in or120005:23
stekernlike verilog coding practices from late 90s, and it being slow and big05:24
stekernand having a more modular pipeline05:27
stekernfun stats from github: http://osrc.dfm.io05:51
stekernolofk: just noticed a difference between the pull requests you've pulled in and the once I pulled in to orpsoc-cores06:00
stekernhint - you don't need to manually go and close the pull request that you merge06:01
stekernhmm, perhaps I was too quick to throw judgement there... the difference is probably because the ones I pulled in involved a merge06:05
stekern...or then not06:07
stekernthe mor1kx-generic pull did not involve a merge, but it still shows as "merged":
olofk_How come I never remember to update that fucking :)06:21
olofk_stekern: And yes. Since I'm cherry-picking instead of merging, I thought I needed to close the requests manually06:24
olofk_#47 was just me being trigger-happy though :)06:24
olofk_I just can't figure out why I can't pull from orpsoc-cores anymore06:25
stekernhmm, ok, maybe you have to then06:25
olofk_A fresh clone works, but I can't have to do that all the time06:25
stekernwhat is it saying?06:26
stekern(Makefile) you need to start keeping more branches around and jumping between them, that will force you to run autoreconf ;)06:27
olofk_I've actually started using branches. Trouble is that I'm not installing fusesoc... despite telling everyone else to do it :(06:42
olofk_(pull problem) It's getting stuck at various percents during the compressing stage (or whatever it's called)06:43
olofk_stekern: Don't know if its' related, but it started after you commited stuff. Could it be some weird incompatibility between git clients, so that your client compresses in a way that my can't read (far-fetched, I know)06:46
stekernoh, sorry, I pushed with the --block-olofk flag ;)06:47
stekerndoes it help if you run git gc?06:47
stekern... with various flags06:48
stekernI've got here06:48
stekernis it only when you pull, or if you try to fetch too?06:53
olofk_Need to try that when I get home07:01
kiwichrisHi, I am Chris from the RTEMS project and I am starting to look over the newlib patches for OpenRisc. Anyone about to answer questions ? I am sorry but I do not know the timezones of devs on this project. I am +10UTC.07:08
stekernkiwichris: I think people are awake07:11
kiwichrisstekern, thanks07:12
kiwichrisjeremybennett, hi07:14
kiwichrisThe RTEMS project has a proposed GSoC project and I am reviewing this patch
kiwichrisThe issue I see is the libgloss support has a GPL 3 license which is not great for newlib as it is typically embedded and statically linked.07:21
stekernmmm, jeremybennett_ is probably the man to comment on that particular issue.07:30
jeremybennett_kiwichris: The libgloss was written as a teaching example, so GPL 3 is appropriate (see If you want a libgloss for commercial deployment, you should write one from scratch.07:38
jeremybennett_Of course if you are building a free and open source embedded system, then GPL 3 is just fine anyway.07:39
kiwichrisThe RTEMS license is GPL2 + runtime exception just like libgcc.07:40
kiwichrisNewlib is typically BSD'ish07:40
jeremybennett_RTEMS is a commercial project, not a teaching example.07:40
kiwichrisRTEMS is not commercial.07:40
kiwichrisIt is an open source project07:41
jeremybennett_Most newlibs, including the ones I write for paying clients are indeed BSD07:41
kiwichrisHmm ok.07:41
jeremybennett_I think you are making the mistake that open source != commercial. Since I make my living by open source == commercial I would dispute this.07:41
jeremybennett_RTEMS is most certainly commercial. People make their living deploying and using it for money.07:42
kiwichrisI am not here for an argument about licenses. If you could refrain from these types of comments I would appreciate it.07:43
jeremybennett_Hold on - you raised the subject!07:44
kiwichrisI asked about the reason for GPL3 in the newlib. I did not need to told what RTEMS is or is not.07:45
jeremybennett_OK - point taken.07:45
jeremybennett_You have the reason - it was written as a teaching example.07:45
kiwichrisjeremybennett_ I will raise the issues of what you say with others and maybe we can conduct a further discussion via email07:47
jeremybennett_kiwichris: Sure - we can have a discussion about licensing separately if you like. As others will tell you, I hold strong views on the subject - evidence above :)07:48
kiwichrisAn that is fine; We have a student in a GSoC project and they should not be subject to these types of issues.07:49
stekernjeremybennett_: to be fair, it wouldn't be completely from scratch, since a lot was based on Jakob Bowers work07:50
jeremybennett_stekern: Well - yes and no. In the end we ditched all of Jakob's actual code. But it was valuable in showing us how to proceed.07:52
kiwichrisRTEMS does not use libgloss so we could remove it; I tend to seek other paths and solution if possible first.07:52
jeremybennett_Hopefully the current libgloss will be used in the same way - to show people the way to go.07:52
jeremybennett_libgloss is purely a board support package. I would strongly encourage anyone to write one suited to their actual needs.07:53
kiwichrisI need to head off; thanks for information07:55
stekernjeremybennett: not trying to be an ass here, but this and this (from has a striking resemblance, so don't say you ditched *all* his code when you didn't.08:16
stekernmy real point is though, you can take his patches and work upon that to get a non-gpl3 libgloss pretty easily08:17
olofk_See, this is the kind of trouble we are going through just because we haven't moved all our coded to MS-pl08:31
olofk_Not super impressed with objcopy right now. There has to be a way to get the verilog backend to generate 32-bit words instead of bytes08:32
olofk_I could of course make my ROM use a byte array, but it feels a bit awkward08:33
stekernmaybe it's better to do the .vmem generation in fusesoc then?09:19
stekernor in orpsoc-cores, with a python-script09:20
stekern...or post a patch to binutils ;)09:22
olofk_binutils patch would be best, but I'll probably go for something in orpsoc-cores to begin with10:05
olofk_Speaking of which, I'm thinking about moving the VerilogWriter class into fusesoc and put it into a utils module. I'm about to use it in a third core now, and want to avoid too much duplication10:06
stekernif you'd use a byte array in the ROM, what would the awkwardness come from? would the ROM need to be byte accessible?10:06
stekernbtw, I got my atlys port compile with your ISE backend10:08
stekernand I got one question, where does the bitgen options come from?10:08
stekernsince it automagically created one10:08
stekerns/one/a .bit file10:08
stekernok, found it in the _cmd.log: bitgen -intstyle ise -f orpsoc_top.ut orpsoc_top.ncd10:13 what startup clocks will that use?10:13
stekernbecause... the startup clock I used in the ise patch I posted wasn't all that great, I needed to powercycle the board everytime I had programmed it10:14
olofk_stekern: You should be able to inject extra options by defining your own tcl_files11:21
olofk_The main reason for choosing the tcl flow instead of the traditional flow was that it seems to be easier to add tcl options rather than adding command line parameters11:22
olofk_Not that I have tried it though. Only used the tools directly before11:22
olofk_Have to figure out where the hell these options are described11:24
stekernyeah, it's probably fine (although I kind of miss having an easy to read Makefile, but that's perhaps due to my tcl blindness more than anything else)11:24
stekern.. and I might add that those bitgen clock options confuses the hell out of me11:24
stekernbitgen -g StartUpClk:JtagClk -w $(DESIGN_NAME)-routed.ncd $(DESIGN_NAME).bit11:29
stekernis what I used to be able to reprogram11:29
olofk_Try something like: project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"11:30
olofk_s/CCLK/JTAG Clock11:31
stekernbut from what I remember from orpsocv2, you need something else for the one that you put onto flash11:31
olofk_ page ~34911:31
olofk_My first version only used xtclsh for the synthesis stage. Main reason for that was that I thought it was easier to read the TCL options than the cryptic names in the XST project file11:32
olofk_Then I realized that I could just run "Generate Programming File" instead of "Syntheis" and get rid of the Makefile11:33
olofk_But yeah. I got a little worried myself when I removed the makefile and let ISE handle things itself. Could go very wrong11:34
stekernhmm, yes this is very informative: "Cclk - Enter Cclk to synchronize to an internal clock provided in the FPGA device"11:37
olofk_I think cclk is some rudimentary RC-based internal clock that is always available11:46
olofk_Perhaps I should convince the Moxie guy to use FuseSoC.11:48
stekernmoxie guy?11:48
olofk_stekern: Have you been hacking on that CPU as well? :)11:48
olofk_A wishbone-compatible hobby CPU11:49
olofk_I think he's the guy who added the verilog support to binutils11:49
stekernoh, right11:51
olofk_I really wish there was a way to clone parts of a GIT repo, svn style, since everyone seems to insist on putting all their crap in the same repo11:57
_franck_web_don't you think we sould have an fusesoc-cores github organization ? So we could put in some non openrisc systems in there12:00
stekernI don't think there's no harm in having such systems under openrisc/orpsoc-cores12:06
olofk_I think it will be good to drop orpsoc from orpsoc-cores at some point, but it's not a big deal right now.12:11
olofk_But when we do, we should probably let them mirror each other for a while. Apparently the orpsoc repo had a few users that were shocked when it was removed :)12:12
Limbolofk_: that's what got submodules are for :p12:15
olofk_Limb: True, but it's a lot more overhead than doing it SVN style12:16
stekernI'm voting for coresnstuff12:17
* Limb was never a big fan of svn12:17
olofk stekern: Do you know how much of the HDMI implementation that is done outside of the FPGA on the Atlys board?17:51
stekernyes, none17:52
olofkBut at least it does SERDES, right?17:52
stekernexcept there are some texas chips on some of the hdmi outputs, but they are only there as "line stabilizer" or something like that17:53
stekernyes, but those are inside the fpga17:53
olofkInteresting. I hadn't looked at it so I just assumed that the spartan6 I/O were way too slow and you needed external transceivers17:53
ysionneauolofk: you can ask lekernel he did manage to get hdmi working (2 outputs at a time) on a spartan 618:08
ysionneauusing the SERDES (SERDES2 ?) ioports18:08
olofkysionneau: That's good to know. Thanks18:09
ysionneauthat's basically the mixxeo project
ysionneauah sorry it's 2 inputs and 1 output18:11
ysionneaunot 2 outputs18:11
-!- Netsplit *.net <-> *.split quits: LoneTech, sfa, blueCmd20:10
olofkMan, these people at Xilinx are stupid20:22
olofkI had the exact same problem as this guy
olofkHe clearly describes the problem, and gets a boilerplate answer that some constructs aren't synthesizable and that they need to see his project files20:26
olofkI'm mainly annoyed because I thought I had found a nice way to create some reusable functions. Worked fine in simulations :(20:39
olofkOh well. It's just the same old truth that it's possible to write good HDL code, but not good HDL code that can be used in several tools20:40
wkoszekolofk: Typically when people ask you to provide a project, it means they way to run it through tools in debugging mode and be able to observe what's really going on.20:42
wkoszekolofk: For simple stuff it's annonying, but it's basically because your bug database has a "How to reproduce" field and you must put something there.20:43
olofkwkoszek: Yes, I can understand that for complex problems, but most of the things I have reported over the years could be proven with very simple test cases20:44
wkoszekolofk: I know. It's mostly because people have lots of stuff to do and given you already have a test case for bug reproduction, they just don't want to waste time writing it.]20:45
wkoszekBut I get what you mean.20:46
olofkAnd I get what you mean as well20:46
olofkI guess it comes down to the fact that neither me nor the support team wants to wrap it up in a package :)20:46
wkoszekIt's typically big corporation bs20:47
Limbwhats the difference between mmuart and uart16550? aka why does the mor1kx-generic have both and can I just include one?20:50
olofkLimb: That's a dirty hack from my side. mmuart is only used for simulations with verilator in that system21:14
olofkThe problem I was trying to solve is that UART is unbearably slow to use in event driven sims (icarus/modelsim), so in those cases I've exchanged the real UART with a UART model21:16
LimbAhh ok21:16
olofkAnd when using verilator the uart16550 core just sends data that can be read out from mmuart and be printed on the screen21:16
LimbOK... So I believe I almost have a working setup here. I need to provide ram though. Am I GOING to have to connect this to on board ram? or is there a core that provides dumbed down ram for me?21:29
olofkLimb: I've been working on exactly that the last couple of days :)21:30
LimbSo short answer is right now, no :P21:31
olofkTo avoid connecting the external RAM on my lx921:31
olofkCan't remember, what FPGA is it you're having?21:31
Limberrr... Artix7 lol21:32
Limbbeen a long day21:32
blueCmdLimb: what are you building? (sorry, I haven't read the backlog)21:33
LimbblueCmd: nothing at this point. just trying to get the processor up and running. Although ultimate end goal is to create a MP3 Player for a design contest I'm in21:33
Limbso possibly booting linux, or coding it by hand if need be21:34
blueCmdLimb: let me know if you want to run Debian on it21:34
blueCmdI have no idea if it would work, but it could be kind of cool21:35
olofkLimb: Try this one
Limbolofk: will do21:37
Limbis that the basic ram implementation you were working on?21:37
LimbAlso, the nexys4 has Cellular ram that the sheets say work the same as SRAM. Would I be able to use the SDRam core to connect to it?21:37
olofkIt's based on ram_wb, but I'm cleaning it up to make it easier to reuse21:38
blueCmd5247 binary packages for Debian or1k built. Getting close to gtk2.0 building21:38
olofkblueCmd: Jesus. That's a lot of package21:40
olofkWhat's the fail rate?21:40
blueCmdolofk: me and mafm has been building stuff :P21:40
blueCmdolofk: of building?21:40
Limbolofk: I hate to be a pain, but how exactly do I go about adding the ram to my system? aka what goes in the top file21:41
blueCmdquite high, debian could be called "Dependency Cycle"21:41
olofkI guess running is a bit harder to determine21:41
blueCmdbut if I get gtk2.0 I can build gcc "the debian way" :)21:41
blueCmd(yes, gcc depends on gtk2.0 in Debian)21:41
blueCmd((for building))21:41
olofkLimb: Something like this
blueCmdolofk: you should use! länge leve sverige!21:42
olofkblueCmd: Hearing that makes me want to keep onto gentoo21:42
blueCmdolofk: yeah, well - you don't want to compile gcc on a 50 MHz DE0 Nano :P21:43
olofkblueCmd: We should just implement gcc in hardware :)21:45
olofkLimb: Have you gotten your interconnects worked out?21:45
blueCmdwhat we SHOULD implement is a 3D accelerator21:45
olofkblueCmd: When I worked at ORSoC we had some guys doing that as their master thesis21:45
blueCmdbut as a CPU extension or something weird21:46
Limbolofk: was just looking at that now. Theres a ram interconnect in here, but i'm not sure what for. basing this off the mor1k-generic example ssytem21:46
blueCmdolofk: did they do the "card" approach? or hooked it up to the wishbone directly?21:46
olofkblueCmd: It's a on-chip core. They were using a digilent atlys21:46
olofkLimb: You could probably use the interconnect from mor1kx-generic without any modifications21:48
olofkBut if you need to add some extra cores it could be good to know that it's autogenerated from a config file21:48
Limbolofk: we're talking wb_intercon.conf and its resulting .v and .vh files right?21:49
blueCmd_franck__: awesome!21:49
olofkLimb: Yes21:49
blueCmd_franck__: what happened with that?21:49
olofkSounds like you're familiar with them already :)21:49
Limbolofk: I have these 2 devices in my slaves list: uart0 and wb_ram021:49
olofkLimb: Sounds right21:50
_franck__blueCmd: they just stopped21:50
Limbolofk: how does the processor know to use the wishbone ram?21:50
olofkblueCmd: It's on opencores. Just that no one else has used it21:50
_franck__there is some bare metal driver for 2D rendering (lines, fill,...)21:50
olofkLimb: CPU starts by reading instructions at address 0x100. Just set up your RAM to cover that area21:51
blueCmdmight be easier to just interface PCIe-cards or older AGP cards or something21:51
LimbAhhhh. I think im starting to understand now21:51
Limb[slave wb_ram0] offset=0 size=8388608 ;8MB21:52
_franck__blueCmd: we need to have a PCIe core for that21:52
olofkblueCmd: There's the open graphics card guys as well. Their mailing list has been awfully quiet for a while now though21:52
Limbwould that be correct olofk21:52
olofkLimb: Yes.21:52
_franck__blueCmd: or we could design a board with some gddr and use the vga_lcd core we have21:53
olofkYes. Doing an external GPU means having a high bandwidth of-chip connection21:54
olofkPCI is probably most feasible with the low-mid-end FPGAs that are supported by the free vendor tools21:54
blueCmdI'm just afraid of the massive amount of work writing the firmware and drivers for the OpenGL stuff21:55
olofkBut on-chip with dedicated RAM like _franck__ said is probably doable21:55
olofkblueCmd: Yeah, it seems like an insane amount of work21:55
blueCmdbut so is OpenRISC :P21:56
_franck__not sure, I took a look at directfb and it's not that massive (don't know if directfb might be a good alternative)21:56
olofkBut perhaps you can start out with a sw renderer and just move a few things in hardware21:56
olofkWe should start with doing a kms driver21:56
blueCmd_franck__: for just a framebuffer - sure, but for OpenGL and hardware accelerated rendering, it will take much effort I recon21:56
olofkI talked to Anton who worked on orgfx and he very much wanted a kms/drm driver, but didn't have time21:57
olofkAnd I think we should skip OpenGL and go directly for eGL21:57
Limbolofk: What is MEM_SIZE_BITS21:58
olofkLimb: log2 of the memory depth21:59
LimbWhat determines the depth? the 8 MB i specified in wishbone?21:59
olofkThe depth specified in wb_intercon.conf will only affect which addresses that are passed through to the RAM22:00
olofkYou have limited memory resources on the FPGA, so I would start with something like 4kB22:00
olofkThat means MEM_SIZE_BITS=12 or 1322:01
olofkor 14? Hmm.. can't count right now22:01
blueCmdolofk: I would love to talk to someone who knows the ins and outs of the open source Radeon driver, they have done what we want I guess22:02
Limblog2(4096) = 1222:02
olofkblueCmd: You should check out ogp if you're interested in this (
Limbolofk: do I have to change the depth in the wb_ram core as well?22:03
olofkMy feeling is that they are a bit too academic though22:03
olofkLimb: Don't think so22:03
olofkSpecifying MEM_SIZE_BITS should be enough22:04
LimbOk. And what should i change my offset for uart to?22:04
Limboffset=0x90000000 seems like it wont exist in 4 KB22:04
olofkLimb: No it won't. That's the address to the UART22:04
Limbso leave it as is?22:05
olofk0x00000000-0x7fffffff are addresses that can be cached, and everything above that should never be cached22:05
blueCmdolofk: and some DRM kernel module (as you said) - might be a fun project.22:06
olofkblueCmd: Yep. Gallium is probably a good starting point22:06
olofkEspecially the llvmpipe driver22:07
Limbwb_m2s_mem_adr <-- I'm assuming the 'mem' is the name of the slave in wishbone?22:08
olofkShould be22:08
Limbguess i should change it back to mem then. thought it had to be wb_ram0 hah22:09
olofkWell, you can name it whatever you want22:09
LimbRight. I thought it had to be named after the instance name22:10
Limbslowly figuring this out :)22:10
olofkGot to sleep now. Good luck22:13
Limbgood night22:13
Limbcan synthesize but nothing seems to be connected22:22
_franck__olofk: don't know if you see it but I updated my pull request. Good night22:28
Limbwhy isnt it including anything22:33
Limbwhat the heck am i missing22:42
Limbstekern: you're not around are you?22:55
blueCmdLimb: I think he's in GMT+2 so I wouldn't count on it22:58
blueCmdor maybe even +3 now with summer time22:58
LimbI can get this system to synthesize... but in reality its just blank. the heirarchy in ISE looks right, but it ends up using no slices22:59
blueCmddo you have input/outputs in the top module? that's the only thing I can think of22:59
blueCmdor that it didn't understand that that is the top module23:00
Limbit knows its the top module23:00
Limb if anyone can take a look and see what im missing I'd appreciate it23:06
--- Log closed Tue Apr 08 00:00:55 2014

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