| --- Log opened Wed Apr 02 00:00:47 2014 | ||
| stekern | _franck__: I've tried something like that before and came to the conclulsion - don't try to do anything fancy in verilog, it won't work | 02:57 |
|---|---|---|
| stekern | because, even if you get it to work, you'll find some stupid tool that it doesn't work with a month later... | 02:57 |
| stekern | for instance, this does works perfectly fine in ISE: http://git.openrisc.net/cgit.cgi/stefan/orpsoc/tree/boards/xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v#n273 | 03:00 |
| stekern | but modelsim can't handle it at all, so I had to open code that loop for it to be satisfied... | 03:01 |
| stekern | your 'ugly' way of doing might actually work in modelsim though | 03:05 |
| stekern | +iy | 03:05 |
| stekern | argh - *it* | 03:05 |
| stekern | which isn't more ugly than the defparam way I used there | 03:06 |
| _franck_web_ | olofk: about my https/proxy issue. It does work in python 3.3. I've never see that before because I may have checked out files using python 3.3 and then made tests with python 2.7.... | 11:36 |
| _franck_web_ | http://bugs.python.org/issue1424152 | 11:36 |
| _franck_web_ | so I won't implement anything in fusesoc to make it work with python 2.7 behind a proxy | 11:37 |
| rah | http://www.bunniestudios.com/blog/?p=3657 | 16:58 |
| stekern | hmm, I suspect I broke something with this... https://github.com/openrisc/orpsoc-cores/commit/5f7cbf7e77a6d54641efc4c832628265a605d1e2 | 18:08 |
| stekern | or more correctly, I didn't cover all the possible cases | 18:10 |
| olofk | Has anyone made a generic wishbone memory except for ram_wb? | 18:36 |
| olofk | I need something that can be mapped to spartan6 block ram, and ram_wb fails because it has async data output | 18:36 |
| stekern | huh, I used that as an SRAM on the sockit | 18:38 |
| olofk | hmm.. | 18:40 |
| olofk | Well, xst can't do anything useful with it | 18:40 |
| olofk | So I figured this would be a good time to finally implement a wb memory with switchable backends for different FPGAs | 18:41 |
| stekern | there is many things xst can't do useful things with | 18:42 |
| stekern | are | 18:42 |
| olofk | True that | 18:42 |
| stekern | http://pastie.org/8989397 | 18:42 |
| stekern | so I think that ^, is the needed follow up to my wb_intercon breaking commit | 18:42 |
| olofk | that code is barely readable, so reviewing a patch takes some time :) | 18:43 |
| olofk | Should had rewritten that a while ago | 18:43 |
| olofk | Hmm.. but I think I see what you're doing there | 18:43 |
| stekern | the whole point is, a wb_mux is now always generated, even if there is only one slave | 18:43 |
| stekern | which IMO is the right thing(tm) to do | 18:44 |
| olofk | Yeah, and I remember you mentioned that in your original commit. I agree that it's correct, and as a bonus it makes the code slightly less complicated | 18:44 |
| stekern | and the point of the first commit was to fix a bug when there was only one master connecting to one slave, then there would be no connections at all made between them | 18:45 |
| stekern | I just didn't think about all the other cases when there are several masters connecting to only one slave :/ | 18:45 |
| olofk | Don't have time to make a thorough review, but feel free to push it if you consider it tested | 18:45 |
| stekern | ...which I *think* is now considered in the follow up patch | 18:46 |
| stekern | I'll test it a bit more, to not extend my shame any further ;) | 18:46 |
| olofk | Ultimately I would like the test bench to generate a few different combinations from .conf files and run tests on them, but it will be a bit complicated to manage that | 18:48 |
| olofk | Right now it only runs unit tests on the arbiter and mux separately | 18:48 |
| olofk | hmm.. might be easier with a systemC test bench | 18:48 |
| olofk | Oh well. That's for the future | 18:49 |
| stekern | yes, that would be good | 18:49 |
| stekern | olofk: btw, shouldn't this https://github.com/openrisc/orpsoc-cores/blob/master/cores/wb_intercon/wb_mux.v#L95 be [`clog2(num_slaves+1)-1:0] | 19:00 |
| stekern | ? | 19:01 |
| stekern | actually, no... it's correct for all values, except num_slaves=1 | 19:06 |
| stekern | hmm, but does that matter? is [-1:0] a valid vector? | 19:20 |
| stekern | it's ugly though... | 19:50 |
| stekern | perhaps something like this: | 19:50 |
| stekern | localparam slave_sel_bits = num_slaves > 1 ? `clog2(num_slaves) : 1; | 19:50 |
| stekern | wire [slave_sel_bits-1:0] slave_sel; | 19:50 |
| stekern | I pushed that + the multimaster, single slave patch | 20:14 |
| stekern | I have a working verilator part of a mor1kx-generic system now too | 20:16 |
| stekern | which thought me that verilator will turn $time into a systemc libcall | 20:20 |
| olofk | Does that libcall thing have any consequences? | 21:29 |
| juliusb | hey fellas | 21:31 |
| juliusb | long time | 21:31 |
| juliusb | you guys have been busy! | 21:32 |
| juliusb | I need to catch up :( | 21:32 |
| olofk | Hi juliusb. Finally out of jail now? | 21:32 |
| juliusb | going to do another ChipHack in May, so I guess I'll need to be on top of it by then | 21:32 |
| juliusb | no, jail decided to promote me and I think they're expecting even more, but more fool them | 21:33 |
| juliusb | hehe | 21:33 |
| juliusb | you guys got windows 7 running on mor1kx yet? | 21:34 |
| olofk | juliusb: No. We've concetrated on OS2/Warp. It is the future of computing | 21:34 |
| juliusb | Of course. | 21:36 |
| juliusb | I've been getting contacted a bit lately about some OpenRISC stuff | 21:36 |
| olofk | Ah. Interesting. Commercial, academical or hobby stuff? | 21:36 |
| juliusb | commerical | 21:36 |
| juliusb | I'm going to get more info, but it sounds like he wants to bankroll a team to do an OR1K-based SoC for use in low cost OLPC-like e-readers, aimed at school kids initially | 21:37 |
| olofk | Sounds like a great project | 21:38 |
| juliusb | well, if only I had 2 lives, i'd jump at it! | 21:38 |
| juliusb | but if I can't, I know others who might like to... | 21:38 |
| olofk | Well you know where to guide him if he wants top notch consultants with OpenRISC experience | 21:38 |
| juliusb | anyway, I like their motivation, they have the right idea, wanting to use as much open source stuff as possible | 21:39 |
| juliusb | oh yeah, I mean, if this thing goes ahead I know who to point him to | 21:40 |
| juliusb | what are you doing these days olofk ? | 21:40 |
| juliusb | rearing your young and hacking? | 21:40 |
| _franck__ | hi juliusb, nice to see you here | 21:40 |
| olofk | Mostly heroin and coke | 21:40 |
| juliusb | _franck__: you too! Did we convince everybody that we should have ORCONF by the seaside where you are this year? | 21:41 |
| olofk | No, but I'm mostly involved with FuseSoC (was ORPSoCv3) together with _franck__ and stekern | 21:41 |
| juliusb | I noticed the rename, makes sense | 21:42 |
| _franck__ | juliusb: I bet you like south of france as you insist on this ;) | 21:42 |
| juliusb | it's warmer and sunnier than the UK! | 21:43 |
| _franck__ | for sure | 21:43 |
| olofk | Not to mention Sweden | 21:43 |
| _franck__ | we can do that during summer/fall and then have some barbecue at the beach | 21:44 |
| juliusb | lovely | 21:44 |
| juliusb | maybe we do that anyway? ;) | 21:44 |
| _franck__ | We have a small conference room so that would be a big organization for me to find a place and stuff | 21:46 |
| _franck__ | and I'm better at hacking | 21:46 |
| juliusb | ah it's called, I believe Stefan Wallentowitz was going to try and arrange it as his uni? | 21:47 |
| juliusb | OK, break time's over, back to my cell. Hopefully they let me out tomorrow and I can talk to you then! | 21:53 |
| _franck__ | :) | 21:53 |
| olofk | Don't drop the soap, and we'll see you later | 21:54 |
| --- Log closed Thu Apr 03 00:00:48 2014 | ||
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